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2020 32nd International Conference on Microelectronics (ICM)最新文献

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Low Power Scalable Ternary Hybrid Full Adder Realization 低功耗可扩展三元混合全加法器的实现
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331500
Mohamed S. Ghoneim, Amr Mohammaden, Rana Hesham, A. Madian
{"title":"Low Power Scalable Ternary Hybrid Full Adder Realization","authors":"Mohamed S. Ghoneim, Amr Mohammaden, Rana Hesham, A. Madian","doi":"10.1109/ICM50269.2020.9331500","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331500","url":null,"abstract":"Multi-level electronic systems offer speed and area simplicity, reducing the complexity of implementation and power dissipation. In this paper, a Hybrid ternary Full Adder (FA) is proposed using Conventional Complementary Metal Oxide Semiconductor (CCMOS), Double Pass-transistor Logic (DPL), and Pass Transistors (PT). The proposed FA is extended up to 64-bits to test scalability. To validate the proposed full adder and calculate its performance analysis, the Cadence Virtuoso toolset is used at technology 130nm with supply voltage 0.9V. An extra transistor is added to overcome the sneak path problem that was detected during the simulation. The ternary values 0, 1, and 2 are represented with 0V, 0.45V and 0.9V respectively. According to the simulation results, the proposed work shows a superior performance, which could be considered a promising alternative for low power applications.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114540106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fractional-order Memristor Emulator with Multiple Pinched Points 具有多个压缩点的分数阶忆阻器仿真器
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331791
Nariman A. Khalil, M. Fouda, L. Said, A. Radwan, A. Soliman
{"title":"Fractional-order Memristor Emulator with Multiple Pinched Points","authors":"Nariman A. Khalil, M. Fouda, L. Said, A. Radwan, A. Soliman","doi":"10.1109/ICM50269.2020.9331791","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331791","url":null,"abstract":"The paper proposes voltage-controlled first- and second-order memristor emulators. The emulators are designed using an operational-transconductance amplifier (OTA) and voltage multiplier blocks plus a fractional-order capacitor. The presented second-order emulator provides two pinched points controlled by order of the employed fractional-order capacitor. Numerical and PSPICE simulation results using AD844 and AD633 are introduced for different cases to validate the theoretical findings. The experimental verification is presented, showing the design flexibility and controllability based on the fractionalorder parameters.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124080498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Variable Gain Amplifier Based on MIFGMOS Transistor for Low Voltage Applications 基于MIFGMOS晶体管的低压可变增益放大器
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331770
I. Abdalla, F. Farag, M. Ibrahim
{"title":"Variable Gain Amplifier Based on MIFGMOS Transistor for Low Voltage Applications","authors":"I. Abdalla, F. Farag, M. Ibrahim","doi":"10.1109/ICM50269.2020.9331770","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331770","url":null,"abstract":"This paper introduces a method for designing a fully balanced Variable Gain Amplifier (VGA) depending on a trans-conductance variation and switched feedback resistance. In this method, the Floating Gate MOS transistor is used as a variable current source. Consequently, the trans-conductance of the gain MOS transistor is varying which is affecting the overall gain. Switching feedback resistance is varying the current which in turn affects the gain range. The proposed strategy is suitable for low voltage applications since the threshold voltage of the floating transistor can be adjusted. Power mitigation and linearity are developed in the variable gain amplifier stage. A simple common source and a fully balanced differential VGA are considered to illustrate the concept. The VGA circuit is designed and simulated using the 0.13μm CMOS process; the overall VGA consumes 1.3mA from a 1.8V supply. The VGA achieves gain variation depending on control voltage and feedback resistance with bandwidth up to 1MHz.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126379483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Controllable OTA Slew-rate for CMOS Image Sensor CMOS图像传感器的可控OTA回转速率
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331502
Ola Ibrahim, Rana Hesham, A. Soltan
{"title":"Controllable OTA Slew-rate for CMOS Image Sensor","authors":"Ola Ibrahim, Rana Hesham, A. Soltan","doi":"10.1109/ICM50269.2020.9331502","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331502","url":null,"abstract":"In this work, a proposed circuit is implemented using tsmc 0.18um technology of area 16642 um2 with supply voltage equals 5V. A proposed implementation of a controllable Operational Transconductance Amplifier (OTA) slew rate for CMOS image sensor (CIS) is proposed. The slew rate is controlled by switching between various bias circuits for the OTA. The biasing circuit controls the value of OTA biased current, which allows controlling the amplifier’s characteristics. As the flicker noise in the main contributor in reducing the quality of image sensors performance. The proposed circuit allows controlling noise effect by increasing the time of reading a pixel signal(OTA slew rate). For reducing the power consumption, the bias cell can be selected regarding the signal to noise ratio (SNR) value.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131776489","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CNTFET-Based Design of Ternary Multiplier using Only Multiplexers 基于cntfet的仅使用多路复用器的三元乘法器设计
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331806
Ramzi A. Jaber, A. Haidar, A. Kassem
{"title":"CNTFET-Based Design of Ternary Multiplier using Only Multiplexers","authors":"Ramzi A. Jaber, A. Haidar, A. Kassem","doi":"10.1109/ICM50269.2020.9331806","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331806","url":null,"abstract":"Multiple-valued logic (MVL) circuit has many-valued logic in each digit to lower interconnections and energy consumption over a binary logic circuit. Therefore, this paper proposes a ternary multiplier (TMUL) that reduce energy consumption in the context of low-power embedded circuits. The CNTFET-based TMUL circuit use only cascading proposed ternary multiplexer to reduce the transistors count and improve performance efficiency. Extensive simulations along with several benchmark designs using HSPICE, prove the merits of the proposed TMUL by reducing energy consumption, improving the noise tolerance, and robustness to process variations (TOX, Channel length, CNT Count, and CNT Diameter).","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133527622","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 26.24uW 9.26-ENOB Dynamic RAM Based SAR ADC for Biomedical Applications 一个26.24uW 9.26-ENOB动态RAM的生物医学应用SAR ADC
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331493
Ola Ibrahim, Rana Hesham, A. Soltan
{"title":"A 26.24uW 9.26-ENOB Dynamic RAM Based SAR ADC for Biomedical Applications","authors":"Ola Ibrahim, Rana Hesham, A. Soltan","doi":"10.1109/ICM50269.2020.9331493","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331493","url":null,"abstract":"This work introduces a new successive approximation register circuit (SAR) for SAR analog to digital converter (ADC) based on Dynamic Random Access Memory (DRAM) cells. Based on the proposed DRAM based SAR ADC and a differential capacitive DAC, a 10-bit 2V ADC is designed in 0.18um CMOS technology. The proposed SAR is compared to traditional SAR to verify that the proposed SAR decreases the power of SAR ADC for biomedical applications. The power consumption for the proposed SAR ADC is found to be 26.24uW with ENOB equal to 9.26, and the maximum sampling frequency is 1MHz. For the traditional SAR ADC the power consumption is 43.56uW and ENOB is 9.3.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"129 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132697940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An ULP Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter 基于ULP电容- dac的恒斜率数字时间转换器
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331506
Kareem R. Rashed, O. Hassan, M. Aboudina, A. Mohieldin, F. Hussien
{"title":"An ULP Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter","authors":"Kareem R. Rashed, O. Hassan, M. Aboudina, A. Mohieldin, F. Hussien","doi":"10.1109/ICM50269.2020.9331506","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331506","url":null,"abstract":"This paper presents a constant-slope digital-to-time converter (CS-DTC) that leverages the concepts of constant-slope charging and charge redistribution to achieve high linearity with ultra-low power consumption (ULP) that makes the proposed DTC suitable for the Internet-of-Things (IoT) applications. The proposed CS-DTC is designed and simulated in 40-nm technology. It draws 8 μA from a 1.1 V supply when clocked at 50 MHz while achieving 3.7 ps resolution over a 7-bit range. A differential nonlinearity (DNL) and an integral nonlinearity (INL) about 0.2 LSB and 0.3 LSB, respectively, are achieved.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127969407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Energy Management Strategy For Grid Connected DC Hybrid Micro Grid Using Particle Swarm Optimization Technique 基于粒子群优化技术的并网直流混合微电网能量管理策略
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331823
Abdel-Aziz Salem, A. El-Shenawy, M. Hamad
{"title":"Energy Management Strategy For Grid Connected DC Hybrid Micro Grid Using Particle Swarm Optimization Technique","authors":"Abdel-Aziz Salem, A. El-Shenawy, M. Hamad","doi":"10.1109/ICM50269.2020.9331823","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331823","url":null,"abstract":"Energy management for micro-grids is a vital issue for the control system. Proper control system should fulfill load demands and ensure system stability with the minimum cost. This paper presents an energy management strategy (EMS) for grid connected DC hybrid micro-grid with cost minimization while considering the dynamics of renewable sources. Modified particle swarm optimization (MPSO) is used to solve the energy management optimization problem. Genetic algorithm (GA) is also used to compare the MPSO result. Hierarchical control is used to combine MPSO with the energy management strategy to enhance MPSO performance and achieve optimum efficiency.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131087296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Collision Probability Computation for Road Intersections Based on Vehicle to Infrastructure Communication 基于车辆与基础设施通信的交叉口碰撞概率计算
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331802
M. Shawki, M. Darweesh
{"title":"Collision Probability Computation for Road Intersections Based on Vehicle to Infrastructure Communication","authors":"M. Shawki, M. Darweesh","doi":"10.1109/ICM50269.2020.9331802","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331802","url":null,"abstract":"In recent years, many probability models proposed to calculate the collision probability for each vehicle and those models used in collision avoidance algorithms and intersection management algorithms. In this paper, we introduce a method to calculate the collision probability of vehicles at an urban intersection. The proposed model uses the current position, speed, acceleration, and turning direction then each vehicle shares its required information to the roadside unit (RSU) via the Vehicle to Infrastructures (V2I). RSU can predict each vehicle’s path in intersections by using the received data. By considering vehicle dimensions in our calculation, RSU will detect a possible collision point and time to collision (TTC) for moving vehicles at the intersection. Simulation results show that this model can detect collisions occurrence early, so it will decrease the probability of a collision occurs.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126756972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
High Throughput Pipelined Implementation of the SHA-3 Cryptoprocessor SHA-3加密处理器的高吞吐量流水线实现
2020 32nd International Conference on Microelectronics (ICM) Pub Date : 2020-12-14 DOI: 10.1109/ICM50269.2020.9331803
Argyrios Sideris, Theodora Sanida, M. Dasygenis
{"title":"High Throughput Pipelined Implementation of the SHA-3 Cryptoprocessor","authors":"Argyrios Sideris, Theodora Sanida, M. Dasygenis","doi":"10.1109/ICM50269.2020.9331803","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331803","url":null,"abstract":"Today, in the modern world of digital communications, sensitive information is transmitted via public networks. It is essential to ensure the privacy of their transmission with confidentiality, security and integrity using techniques like hashing. An optimized and high throughput implementation of Secure Hash Algorithm-3 (SHA-3) in hardware is a vital issue for the efficient operation of many modern and demanding systems that utilize this operation in high bandwidth links. In this paper, we propose a pipelined architecture of the SHA-3 256 algorithm in order to increase the hash function calculation speed in Field Programmable Gate Array (FPGA). The proposed architecture is able to function in both single block and multi block messages. Our design is designed and verified in the Very High Speed Integrated Circuit Hardware Description language (VHDL) and synthesized in the FPGA Arria 10 GX. The results show that a significant improvement in throughput, frequency and efficiency is achieved compared to the published literature.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126771819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
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