An ULP Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter

Abstract

This paper presents a constant-slope digital-to-time converter (CS-DTC) that leverages the concepts of constant-slope charging and charge redistribution to achieve high linearity with ultra-low power consumption (ULP) that makes the proposed DTC suitable for the Internet-of-Things (IoT) applications. The proposed CS-DTC is designed and simulated in 40-nm technology. It draws 8 μA from a 1.1 V supply when clocked at 50 MHz while achieving 3.7 ps resolution over a 7-bit range. A differential nonlinearity (DNL) and an integral nonlinearity (INL) about 0.2 LSB and 0.3 LSB, respectively, are achieved.