M. Bensenouci, Mohamed Ali, H. Escid, Y. Savaria, M. Sawan
{"title":"A VCO-Based Nonuniform Sampling ADC Using a Slope-Dependent Pulse Generator","authors":"M. Bensenouci, Mohamed Ali, H. Escid, Y. Savaria, M. Sawan","doi":"10.1109/ICM50269.2020.9331795","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331795","url":null,"abstract":"This paper presents a voltage-controlled oscillator (VCO)-based nonuniform sampling analog-to-digital converter (ADC) as an alternative to the level-crossing (LC)-based converters for digitizing biopotential signals. This work aims to provide a good signal-to-noise-and-distortion ratio at a low average sampling rate. In the proposed conversion method, a slope-dependent pulse generation block is used to provide a variable sample rate adjusted according to the input signal’s slope. Simulation results show that the introduced method meets a target reconstruction quality with a sampling rate approaching 92 Sps, while on the same MIT-BIH Arrhythmia N 106 ECG benchmark, the classic LC-based approach requires a sampling rate higher than 500 Sps. The benefits of the proposed method are more remarkable when the input signal is very noisy. The proposed ADC achieves a compression ratio close to 4, but with only 5.4% root-mean-square difference when tested using the MIT-BIH Arrhythmia Database.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125943520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
G. Pappas, Vassilis Alimisis, Christos Dimas, P. Sotiriadis
{"title":"Analogue Realization of a Fully Tunable Fractional-Order PID Controller for a DC Motor","authors":"G. Pappas, Vassilis Alimisis, Christos Dimas, P. Sotiriadis","doi":"10.1109/ICM50269.2020.9331798","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331798","url":null,"abstract":"This paper explores a new integrated-circuit architecture of an analog, active, tunable and selectively fractional or integer-order PID controller using operational amplifiers. Controller’s major parameters are tuned via appropriate DC currents to the desired values. The proposed architecture is validated in a case study of a DC motor control and it can be used as a building block in industrial and commercial control systems. Circuit and physical design (layout) have been done in TSMC 90nm CMOS process. Extensive circuit and post-layout simulation are carried out using the Cadence IC design.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126860755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Threshold Switch Modeling for Analog CAM Design","authors":"Jinane Bazzi, M. Fouda, R. Kanj, A. Eltawil","doi":"10.1109/ICM50269.2020.9331775","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331775","url":null,"abstract":"In this work, we develop a model for a threshold switching device to be used in the context of an analog CAM design. For this, we tune and optimize a two-terminal hysteretic device model that relies on a state variable to capture proper behavior in different operating conditions. It satisfies a 1 mV/decade ON switching slope. We study the model sensitivities in the context of device charging a capacitor and an analog CAM cell switching between match and mismatch states. We also study the impact of variations in the device hold and switching voltage parameters on the analog search interval.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122359955","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Low-Power 0.4–2.3GHz NB-IoT UE Receiver with −15dBm OOB-Tolerant RF Front End","authors":"Hassan Ali, A. Mohieldin, M. Aboudina","doi":"10.1109/ICM50269.2020.9331505","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331505","url":null,"abstract":"This paper presents the system and circuit level design of a NB-IoT receiver (RX) based on 3GPP Technical Specification (TS) 36.101. This design targets serving many NB-IoT operation bands, so no off-chip filter is used. This dictates large linearity specification on the RF front end to avoid desensitization by −15dBm out-of-band blockers (OOBs). Large linearity specification leads to large power consumption. A solution is proposed to reduce power consumption of the RF front end, while achieving high gain and high linearity. The proposed RF front end provides 29.5dB gain and −10.9dBm IIP3 while consuming 2mW from a single 1.1V power supply. The solution includes adding gain programmability to conventional resistive feedback LNA to relax the trade-off between linearity and power consumption. The RF front end is designed using a 40nm CMOS technology and occupies an area of 0.2mm2.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114263838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Mohamed H. Abdulmonem, Jihad EssamEddeen, Michael H. Zakhari, S. Hanafi, H. Mostafa
{"title":"Hardware Acceleration of Dash Mining Using Dynamic Partial Reconfiguration on the ZYNQ Board","authors":"Mohamed H. Abdulmonem, Jihad EssamEddeen, Michael H. Zakhari, S. Hanafi, H. Mostafa","doi":"10.1109/ICM50269.2020.9331815","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331815","url":null,"abstract":"Dynamic Partial Reconfiguration (DPR) enables reconfiguration of FPGA parts at runtime to provide flexible hardware accelerators with advantages in area, power, reconfiguration time, and memory utilization. In this paper, a design employing DPR technology is proposed to accelerate the mining of the cryptocurrency DASH using the PCAP controller on the ZYNQ 702 Evaluation Board. The DPR design remarkably reduces the area needed for implementing the hash of the mining process of dash on the ZYNQ 702 board.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128857390","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Highly-Reliable Approximate Quadruple Modular Redundancy with Approximation-Aware Voting","authors":"Mahmoud Masadeh, Alain Aoun, O. Hasan, S. Tahar","doi":"10.1109/ICM50269.2020.9331771","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331771","url":null,"abstract":"Redundancy has been a general method to produce a fault-tolerance system. The Triple Modular Redundancy (TMR) with majority voters covers 100% single fault-masking, where the minimum area overhead is 200%. On the other hand, approximate computing is suitable for applications that can tolerate errors and imprecision in their underlying computations. Thus, inexact results allow reducing the computational complexity and hardware requirements with increased performance and power efficiency. This work explains how approximate computing could provide low-cost fault-tolerant architectures with an enhanced system’s reliability. In particular, we implement a novel Quadruple Modular Redundancy (QMR) designs using three identical approximate modules in addition to the exact module. Moreover, a two-steps magnitude-based voter is proposed to be able to tolerate approximation error. To validate our approach, we conducted experiments and the results showed the ability to achieve high fault tolerance, i.e., 99.88%, while reducing the probability of system failure by 15%, with 62% and 49.5% reduced area and power, respectively, compared to the traditional TMR.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127808748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Energy Efficient Clustering Protocols for WSN: Performance Analysis of FL-EE-NC with LEACH, K Means-LEACH, LEACH-FL and FL-EE/D using NS-2","authors":"KS FathimaShemim, U. Witkowski","doi":"10.1109/ICM50269.2020.9331768","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331768","url":null,"abstract":"Wireless Sensor Networks playing an important role in applications where human interaction is difficult. WSN is extensively used in real-time applications like surveillance systems, environmental monitoring systems, disaster management and health monitoring, etc. Since sensor nodes are deployed in isolated areas, recharging or replacing node batteries is difficult. So for the better performance of the network, it’s important to improve network lifetime by increasing sensor nodes’ energy efficiency. Data aggregation methods and energy-efficient routing algorithms have an important role in WSN to tackle the problem with network lifetime. Hierarchical energy-efficient routing protocols are trending in the WSN research field, which helps to improve overall network lifetime by increasing the lifetime of sensor nodes by minimizing the energy consumption of each node in the network. In this paper, compared and investigated the performance of the Fuzzy Logic-Network Coding-Energy Efficient (FL-NC-EE) routing protocol with the other energy-efficient clustering protocols like LEACH, LEACH-FL, K Means-LEACH and FL-EE/D using NS2. The result shows that the FL-NC-EE protocol outperforms in terms of energy efficiency and network lifetime compared to the other protocols discussed in this paper.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122170612","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Hardware Implementation of Floating Point Matrix Inversion Modules on FPGAs","authors":"S. Chetan, J. Manikandan, V. Lekshmi, S. Sudhakar","doi":"10.1109/ICM50269.2020.9331796","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331796","url":null,"abstract":"Matrices are employed for diversified applications such as image processing, control systems, video processing, radar signal processing, compressive sensing and many more. Finding inverse of a floating point large scale matrix is considered to be computationally intensive and their hardware implementation is still a research topic. FPGA implementation of four different floating-point matrix inversion algorithms using a novel combination of high level language programming and model based design is proposed in this paper. The proposed designs can compute inverse of a floating point matrix up to a matrix size of 25×25 and can be easily scaled to large size matrices. The performance evaluation of proposed matrix inversion modules are carried out by their hardware implementation on a Zynq 7000 FPGA based ZED board and the results are reported.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130813589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
T. Zengerle, J. Joppich, H. Lensch, A. Ababneh, H. Seidel
{"title":"A Lumped Element Model for the Damping Mechanism of Micro-oscillators in the Transitional Flow Regime","authors":"T. Zengerle, J. Joppich, H. Lensch, A. Ababneh, H. Seidel","doi":"10.1109/ICM50269.2020.9331778","DOIUrl":"https://doi.org/10.1109/ICM50269.2020.9331778","url":null,"abstract":"This study presents a Lumped Element Model (LEM) for the different damping mechanisms of micro-oscillators oscillating in a gas medium near a boundary. The LEM is based on resistive and inductive components as well as on a newly introduced inductive constant phase element (CPE). The model is applied to experimental data of micro-oscillators for six different gas atmospheres and gap widths to a limiting boundary in-between 150 to 3500 μm. The LEM is in good agreement with the experimental data of the first four bending modes and the electronic components exhibit a reasonable correlation to the physical properties of the measured gases.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121344188","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}