G. Pappas, Vassilis Alimisis, Christos Dimas, P. Sotiriadis
{"title":"Analogue Realization of a Fully Tunable Fractional-Order PID Controller for a DC Motor","authors":"G. Pappas, Vassilis Alimisis, Christos Dimas, P. Sotiriadis","doi":"10.1109/ICM50269.2020.9331798","DOIUrl":null,"url":null,"abstract":"This paper explores a new integrated-circuit architecture of an analog, active, tunable and selectively fractional or integer-order PID controller using operational amplifiers. Controller’s major parameters are tuned via appropriate DC currents to the desired values. The proposed architecture is validated in a case study of a DC motor control and it can be used as a building block in industrial and commercial control systems. Circuit and physical design (layout) have been done in TSMC 90nm CMOS process. Extensive circuit and post-layout simulation are carried out using the Cadence IC design.","PeriodicalId":243968,"journal":{"name":"2020 32nd International Conference on Microelectronics (ICM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-12-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 32nd International Conference on Microelectronics (ICM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM50269.2020.9331798","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
This paper explores a new integrated-circuit architecture of an analog, active, tunable and selectively fractional or integer-order PID controller using operational amplifiers. Controller’s major parameters are tuned via appropriate DC currents to the desired values. The proposed architecture is validated in a case study of a DC motor control and it can be used as a building block in industrial and commercial control systems. Circuit and physical design (layout) have been done in TSMC 90nm CMOS process. Extensive circuit and post-layout simulation are carried out using the Cadence IC design.