CNTFET-Based Design of Ternary Multiplier using Only Multiplexers

Abstract

Multiple-valued logic (MVL) circuit has many-valued logic in each digit to lower interconnections and energy consumption over a binary logic circuit. Therefore, this paper proposes a ternary multiplier (TMUL) that reduce energy consumption in the context of low-power embedded circuits. The CNTFET-based TMUL circuit use only cascading proposed ternary multiplexer to reduce the transistors count and improve performance efficiency. Extensive simulations along with several benchmark designs using HSPICE, prove the merits of the proposed TMUL by reducing energy consumption, improving the noise tolerance, and robustness to process variations (TOX, Channel length, CNT Count, and CNT Diameter).