High Throughput Pipelined Implementation of the SHA-3 Cryptoprocessor

Today, in the modern world of digital communications, sensitive information is transmitted via public networks. It is essential to ensure the privacy of their transmission with confidentiality, security and integrity using techniques like hashing. An optimized and high throughput implementation of Secure Hash Algorithm-3 (SHA-3) in hardware is a vital issue for the efficient operation of many modern and demanding systems that utilize this operation in high bandwidth links. In this paper, we propose a pipelined architecture of the SHA-3 256 algorithm in order to increase the hash function calculation speed in Field Programmable Gate Array (FPGA). The proposed architecture is able to function in both single block and multi block messages. Our design is designed and verified in the Very High Speed Integrated Circuit Hardware Description language (VHDL) and synthesized in the FPGA Arria 10 GX. The results show that a significant improvement in throughput, frequency and efficiency is achieved compared to the published literature.