2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)最新文献_第6页

Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization 稀疏矩阵LU分解的区域高效高吞吐量架构实现

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981319

G. P. Kumar, Chinthala Ramesh

{"title":"Implementation of an Area Efficient High Throughput Architecture for Sparse Matrix LU Factorization","authors":"G. P. Kumar, Chinthala Ramesh","doi":"10.1109/IEMENTech48150.2019.8981319","DOIUrl":"https://doi.org/10.1109/IEMENTech48150.2019.8981319","url":null,"abstract":"In many scientific computations, Lower-upper (LU) decomposition is an important computing step, as most of the scientific applications are modeled using linear equations Ax=b. The Linear equations are used in our everyday life applications such as profit prediction in the business, income over time, mileage rate calculation. The complexity of data makes difficult to parallelize the LU decomposition. Because parallelization of LU decomposition improves the speed of solving LU factorization and reduces the delay in critical applications range from weather forecasting to power system problems-load flow computation. Field Programmable Gate Array (FPGA) is having more logic resources and parallel computing to speed up the matrix decomposition. In this work an area efficient High Throughput Architecture is designed for Sparse Matrix LU factorization by changing/modifying the computing steps in algorithm. The problem with the KLU algorithm is it occupies more area and the throughput is less when compared with the modified KLU algorithm. The area is reduced by the 10%. The hardware complexity of implementation of sparse LU Factorization on FPGA is 15% less when compared with CPU & GPU [4] and also the computing efficiency i.e., throughput 10% to 12% on GPU&CPU do not reach theoretical computing efficiency (theoretical peak throughput).The hardware efficiency (typically 1 to 4%) of UMFPACK and SuperLU, are very less due to poor utilization of Floating point.","PeriodicalId":243805,"journal":{"name":"2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)","volume":"194 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114201448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Novel Design of a Wideband Microwave Absorber at Ku and K Bands Ku和K波段宽带微波吸收器的新设计

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981045

Priyanka Das, Dipankar Saha, Mouli Ghosh, Shambo Mukherjee, Samayeta Chattopadhyay

引用次数: 0

Study and Investigation of DC and RF Performance of TFET on SEL-BOX and Conventional SOI TFET with SiO2/HfO2 Stacked Gate Structure 基于SiO2/HfO2堆叠栅极结构的SEL-BOX和传统SOI TFET直流和射频性能研究

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981284

A. K. Singh, Dhruvajyoti Barah, M. Tripathy, K. Baral, S. Chander, P. Singh, S. Jit

引用次数: 2

Modeling of Pretreatment Process of Lignocellulosic Biomass by Dilute Acid Hydrolysis 木质纤维素生物质稀酸水解预处理过程建模

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981124

Sayan Chatteriee, A. Ghosh, Talha Khan, Soumyadip Roy, Ayan Chatterjee, Mainak Biswas

{"title":"Modeling of Pretreatment Process of Lignocellulosic Biomass by Dilute Acid Hydrolysis","authors":"Sayan Chatteriee, A. Ghosh, Talha Khan, Soumyadip Roy, Ayan Chatterjee, Mainak Biswas","doi":"10.1109/IEMENTech48150.2019.8981124","DOIUrl":"https://doi.org/10.1109/IEMENTech48150.2019.8981124","url":null,"abstract":"The most important renewable energy resources is biomass, which is one of the leading cause to reduce the dependence on fossil fuels and emission of CO2. Ethanol, converted from cellulose and hemicellulose in lignocellulosic biomass by biochemical technology, has a great potential to substitute, at least partly, the conventional gasoline as transportation fuels. Hemicellulose contains abundant fermentable five carbon sugars, which can be released by thermal/chemical pre-treatment processes. The dilute acid pretreatment is a highly efficient process, which can easily hydrolyse hemicellulose to monomeric xylose to make it more sensitive to enzymatic digestion to produce ethanol. In this study, a model has been developed for the hydrolysis of hemicellulose to its xylooligomers and finally xylose using a first order reaction system. This model represents oligomers as different compounds and the effects of variation in acid content and temperature on oligomer production have been studied in this work. A comparison of optimum production of xylose from different biomass has been made in this study.","PeriodicalId":243805,"journal":{"name":"2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116942179","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

A Comparative Study of Z- Transform and Fourier Transform applied on Medical Images for Detection of Cancer Segments Z-变换与傅里叶变换在医学图像癌症片段检测中的比较研究

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981005

Soumen Santra, Surajit Mandal, Kunal Das, J. Bhattacharjee, A. Deyasi

引用次数: 3

Assessement of Single Stage Three Phase Boost Inverter for an Islanded Microgrid 孤岛微电网单级三相升压逆变器性能评估

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981143

P. Arvind, Deepak Kumar, P. Thakura

引用次数: 0

Wideband HMSIW Band Pass Filter design using H-shaped Periodic Structures 基于h型周期结构的宽带HMSIW带通滤波器设计

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981175

S. Moitra, J. Mishra, I. Aarya

引用次数: 0

Ni0.1CO0.9Fe2O4 spinel ferrite as a promising magneto-dielectric substrate for X-band Microstrip Patch Antenna Ni0.1CO0.9Fe2O4尖晶石铁氧体作为x波段微带贴片天线的有前途的磁介质衬底

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981054

K. Pubby, S. R. Bhongale, P. Vasambekar, S. B. Narang

{"title":"Ni0.1CO0.9Fe2O4 spinel ferrite as a promising magneto-dielectric substrate for X-band Microstrip Patch Antenna","authors":"K. Pubby, S. R. Bhongale, P. Vasambekar, S. B. Narang","doi":"10.1109/IEMENTech48150.2019.8981054","DOIUrl":"https://doi.org/10.1109/IEMENTech48150.2019.8981054","url":null,"abstract":"In the present study, the suitability of Ni-Co spinel ferrites as dielectric substrate for microstrip patch antenna has been reconnoitered in X-band frequency range. The scrutinized spinel ferrites with chemical composition Ni1. xCoxFe2O4(x=0.00,0.30,0.60,0.90) were synthesized using Pechini's sol gel method. For the present study, Ansoft Designer SV2 was used to design and analyze the microstrip patch antenna. Simulation of antenna was done at resonant frequency of 10.02 GHz, which makes this research to find application in military and surveillance. Firstly, the antenna dimensions were calculated using resonant frequency and electromagnetic properties of the compositions. The antenna output parameters such as return loss, bandwidth, VSWR (Voltage Standing Wave Ratio), Smith Chart and radiation pattern were subsequently analyzed by the simulation Based on the analysis, Ni-Co ferrite Ni0.l Co0.9Fe2O4has come out to be the best alternative out of the studied compositions for its possible usage as efficient dielectric substrate in microstrip patch antenna in 8.2 – 12.4 GHz frequency range.","PeriodicalId":243805,"journal":{"name":"2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132118433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Design of Smart System for Detecting Proximity of Obstacles at Acute and Obtuse Angles 锐角和钝角障碍物接近度智能检测系统的设计

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981066

Poulami Adhikary, Naina Gupta, A. Halder, A. Deyasi

引用次数: 1

Logic Encryption of Combinational Circuits 组合电路的逻辑加密

2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech) Pub Date : 2019-08-01 DOI: 10.1109/IEMENTech48150.2019.8981198

K. Pritika, M. Vinodhini

{"title":"Logic Encryption of Combinational Circuits","authors":"K. Pritika, M. Vinodhini","doi":"10.1109/IEMENTech48150.2019.8981198","DOIUrl":"https://doi.org/10.1109/IEMENTech48150.2019.8981198","url":null,"abstract":"Logic encryption for combinational circuits are proposed in this paper. Logic encryption is achieved by using key gate transistors in the circuit schematic of subtractors and adders. In this work, two logic encrypted full adder and subtractor circuits and half adder and half subtractor circuits using logic encrypted gates are designed and proposed. Of the two proposed circuits for adders and subtractors, one is strong logic encrypted than the other. All the encrypted adders and subtractors are compared with conventional adders and subtractors for logic encryption level and various other parameters like area and power. The results show improvement in area and power. The proposed half adder has 42% more area and 26.02% more power and half subtractor has 50% more area and 24.4% more power than the existing circuits. The proposed full adder has 25% less area (transistor count) and 33% less power consumption and the proposed full subtractor is also better in terms of area and power consumption with 30% and 24% lesser. Even strong logic encrypted full adder and full subtractor are proposed in this work. Full adder and subtractor have 22% increase in area each and on an average 2.3% increase in power each respectively.","PeriodicalId":243805,"journal":{"name":"2019 3rd International Conference on Electronics, Materials Engineering & Nano-Technology (IEMENTech)","volume":"104 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132154706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1