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38th International Symposium on Multiple Valued Logic (ismvl 2008)最新文献

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Encoding Max-CSP into Partial Max-SAT 将Max-CSP编码为Partial Max-SAT
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.22
Josep Argelich, Alba Cabiscol, I. Lynce, F. Manyà
{"title":"Encoding Max-CSP into Partial Max-SAT","authors":"Josep Argelich, Alba Cabiscol, I. Lynce, F. Manyà","doi":"10.1109/ISMVL.2008.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.22","url":null,"abstract":"We define a number of original encodings that map Max-CSP instances into Partial Max-SAT instances. Our encodings rely on the well-known direct and support encodings from CSP into SAT. Then, we report on an experimental investigation that was conducted to compare the performance profile of our encodings on random binary Max-CSP instances. Moreover, we define a new variant of the support encoding from CSP into SAT which produces fewer clauses than the standard support encoding.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115887330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Multiple Valued Logic Using 3-State Quantum Dot Gate FETs 基于三态量子点门场效应管的多值逻辑
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.34
J. Chandy, F. Jain
{"title":"Multiple Valued Logic Using 3-State Quantum Dot Gate FETs","authors":"J. Chandy, F. Jain","doi":"10.1109/ISMVL.2008.34","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.34","url":null,"abstract":"This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a transistor with a stable \"intermediate\" state, where the drain current remains constant over a range of input gate voltages due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Using this model, we have designed rudimentary logic circuits for use in multiple-valued logic circuits.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133138272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions 混合Reed-Muller Haar变换及其在逻辑函数谱表示约简中的应用
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.8
S. Minasyan, J. Astola, K. Egiazarian, R. Stankovic
{"title":"Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions","authors":"S. Minasyan, J. Astola, K. Egiazarian, R. Stankovic","doi":"10.1109/ISMVL.2008.8","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.8","url":null,"abstract":"In this paper we present a new hybrid transform based on the Kronecker product of Reed-Muller and Reed-Muller Haar transforms. The proposed transform shares attractive properties of both Reed-Muller transform and Reed-Muller Haar transform. An example of application of hybrid transform for reduction of the number of nonzero coefficients in spectra of truth vectors of switching functions is presented. The experiments show that the proposed approach, on average, reduces the number of nonzero coefficients in the spectra of benchmark functions.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design of High-Performance Quaternary Adders Based on Output-Generator Sharing 基于输出-发生器共享的高性能四元加法器设计
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.11
H. Shirahama, T. Hanyu
{"title":"Design of High-Performance Quaternary Adders Based on Output-Generator Sharing","authors":"H. Shirahama, T. Hanyu","doi":"10.1109/ISMVL.2008.11","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.11","url":null,"abstract":"Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs). Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations. The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders. For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124351451","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 38
Quantum Logic Implementation of Unary Arithmetic Operations 一元算术运算的量子逻辑实现
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.27
M. Thornton, D. Matula, L. Spenner, D. M. Miller
{"title":"Quantum Logic Implementation of Unary Arithmetic Operations","authors":"M. Thornton, D. Matula, L. Spenner, D. M. Miller","doi":"10.1109/ISMVL.2008.27","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.27","url":null,"abstract":"The mathematical property of inheritance for certain unary fixed point operations has recently been exploited to enable the efficient formulation of arithmetic algorithms and circuits for operations such as the modular multiplicative inverse, exponentiation, and discrete logarithm computation in classical binary logic circuits. This principle has desirable features with regard to quantum logic circuit implementations and is generalized for the case of MVL arithmetic systems. It is shown that the inheritance principle in conjunction with the bijective nature of many unary functions is used to realize compact quantum logic cascades that require no ancilla digits and generate no garbage outputs.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114926967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Comparative Study by Solving the Test Compaction Problem 解决试验压实问题的比较研究
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.17
D. Logofătu, R. Drechsler
{"title":"Comparative Study by Solving the Test Compaction Problem","authors":"D. Logofătu, R. Drechsler","doi":"10.1109/ISMVL.2008.17","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.17","url":null,"abstract":"Beside issues like the low power dissipation and the increase of defect coverage, test compaction is an important requirement regarding large scale integration (LSI) testing. The overall cost of a VLSI circuit's testing depends on the length of its test sequence; therefore the reduction of this sequence, keeping the coverage, will lead to a reduction of used resources in the testing process. In this paper we study test vectors over a five-valued logic. The problem of finding minimal test sets is NP-complete. Consequently, an optimal algorithm has limited practical use and is only applicable to small problem instances. We describe three approaches for reducing the length of test sequences: an optimal algorithm using a recursive backtracking method (OPT) and two greedy algorithms (GRNV and GRBT). The behavior of these algorithms is discussed and analyzed by experiments. Finally, directions for future work are given.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"100 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126705291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter 一种3/7电平混合模式算法模数转换器
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.25
Kazuki Akutagawa, K. Machida, T. Waho
{"title":"A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter","authors":"Kazuki Akutagawa, K. Machida, T. Waho","doi":"10.1109/ISMVL.2008.25","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.25","url":null,"abstract":"A 3/7-level mixed-mode algorithmic analog-to- digital converter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-mum CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB (ap7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from conventional 3-level and 7-level algorithmic ADCs.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115511642","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit 基于延迟表的大规模多值电流模式电路高速时序验证方案
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.12
T. Nagai, N. Onizawa, T. Hanyu
{"title":"High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit","authors":"T. Nagai, N. Onizawa, T. Hanyu","doi":"10.1109/ISMVL.2008.12","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.12","url":null,"abstract":"A high-speed timing verification scheme using delay tables is proposed for a large-scaled multiple-valued current- mode (MVCM) circuit. A multi-level input-signal transition in the MVCM circuit is decomposed of binary signal transitions whose behaviors are represented using delay tables as higher abstracted description than transistor-level one. This high-level abstraction makes it possible to greatly improve the timing-verification speed of the MVCM circuit. It is demonstrated that the timing-verification speed for a 32-digit radix-2 signed-digit adder in the proposed method is about 1000-times faster than that in a conventional HSPICE-based approach with maintaining high delay-estimation accuracy.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115675800","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Betweenness, Metrics and Entropies in Lattices 格中的间隔性、度量和熵
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.21
D. Simovici
{"title":"Betweenness, Metrics and Entropies in Lattices","authors":"D. Simovici","doi":"10.1109/ISMVL.2008.21","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.21","url":null,"abstract":"We investigate a class of metrics on lattices that are compatible with the partial order defined by the lattice using the ternary relation of betweenness that can be naturally defined on a metric space. The relationships between entropy-like functions and metrics defined on lattices are studied and we show the links that exists between various properties of entropies and properties of metrics. Applications to metrics defined on the lattice of partitions of finite sets are examined.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122395877","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Majority and Other Polynomials in Minimal Clones 最小克隆中的多数多项式和其他多项式
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.38
Hajime Machida, Tamás Waldhauser
{"title":"Majority and Other Polynomials in Minimal Clones","authors":"Hajime Machida, Tamás Waldhauser","doi":"10.1109/ISMVL.2008.38","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.38","url":null,"abstract":"A minimal clone is an atom of the lattice of clones. A minimal function is, briefly saying, a function which generates a minimal clone. For a prime power k we consider the base set with k elements as a finite field GF(k). We present binary idempotent minimal polynomials and ternary majority minimal polynomials over GF(3) and generalize them to minimal polynomials over GF(k) for any prime power k ges3.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128193682","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
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