{"title":"一种3/7电平混合模式算法模数转换器","authors":"Kazuki Akutagawa, K. Machida, T. Waho","doi":"10.1109/ISMVL.2008.25","DOIUrl":null,"url":null,"abstract":"A 3/7-level mixed-mode algorithmic analog-to- digital converter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-mum CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB (ap7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from conventional 3-level and 7-level algorithmic ADCs.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter\",\"authors\":\"Kazuki Akutagawa, K. Machida, T. Waho\",\"doi\":\"10.1109/ISMVL.2008.25\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 3/7-level mixed-mode algorithmic analog-to- digital converter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-mum CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB (ap7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from conventional 3-level and 7-level algorithmic ADCs.\",\"PeriodicalId\":243752,\"journal\":{\"name\":\"38th International Symposium on Multiple Valued Logic (ismvl 2008)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"38th International Symposium on Multiple Valued Logic (ismvl 2008)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2008.25\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2008.25","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
提出了一种3/7电平混合模算法模数转换器(ADC)。该操作包括六个阶段,以获得8位分辨率。前三个相位采用3电平模式,实现精确转换,后三个相位采用7电平模式,提高采样速度。采用0.18 μ m CMOS技术,电源电压为1.8 V,进行晶体管级仿真,评估电路性能。在12.8 MHz的采样频率下获得48.1dB (ap7.7 bit)的信噪比,优于传统的3电平和7电平算法adc。
A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter
A 3/7-level mixed-mode algorithmic analog-to- digital converter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-mum CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB (ap7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from conventional 3-level and 7-level algorithmic ADCs.