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38th International Symposium on Multiple Valued Logic (ismvl 2008)最新文献

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Permutations under Spectral Transforms 谱变换下的排列
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.16
C. Moraga
{"title":"Permutations under Spectral Transforms","authors":"C. Moraga","doi":"10.1109/ISMVL.2008.16","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.16","url":null,"abstract":"The paper studies the conditions under which permutations on the truth vector of a multiple-valued function are preserved under a spectral transform. Both the cases of the Vilenkin-Chrestenson and of the Generalized Reed Muller transforms are discussed. One condition to preserve a permutation is that the corresponding permutation matrix is self-similar under the transform matrix.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114992056","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices 利用TMR器件实现多值电流模式电路的v值变化补偿
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.13
Akihiro Hirosaki, M. Miura, Atsushi Matsumoto, T. Hanyu
{"title":"Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices","authors":"Akihiro Hirosaki, M. Miura, Atsushi Matsumoto, T. Hanyu","doi":"10.1109/ISMVL.2008.13","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.13","url":null,"abstract":"A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126642239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On Fixed Points and Cycles in the Reed Muller Domain Reed Muller定义域上的不动点和不动环
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.15
C. Moraga, S. Stojkovic, R. Stankovic
{"title":"On Fixed Points and Cycles in the Reed Muller Domain","authors":"C. Moraga, S. Stojkovic, R. Stankovic","doi":"10.1109/ISMVL.2008.15","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.15","url":null,"abstract":"This paper studies cycles that appear by repeatedly applying the RM transform to a p-valued function. It is shown that there are nontrivial fixed points, which correspond to eigenvectors of the transform and a simple method is proposed to determine the maximum period of n-place functions for a given p. The concept of spectral diversity is introduced, which may be applied to characterize p-valued functions.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114420878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits 四元解码器、多路复用器和多路复用器电路的可逆实现
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.33
Mozammel H. A. Khan
{"title":"Reversible Realization of Quaternary Decoder, Multiplexer, and Demultiplexer Circuits","authors":"Mozammel H. A. Khan","doi":"10.1109/ISMVL.2008.33","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.33","url":null,"abstract":"Quaternary logic is very suitable for encoded realization of binary logic functions by grouping 2-bits together into quaternary digits. This sort of quaternary encoded reversible realization of binary logic function requires half times input/output lines than the original binary reversible realization. Quaternary decoder, multiplexer, and demultiplexer are very important building blocks of quaternary digital systems. In this paper, we show reversible realization of these circuits using quaternary reversible gates like quaternary shift gates (QSG), quaternary controlled shift gates (QCSG), and quaternary Toffoli gates (QTG). We also show the realization of multi-digit QCSG and QTG using QSG and QCSG, which are realizable using liquid ion-trap quantum technology and other reversible technologies.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129685960","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 34
Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups 有限非阿贝尔群上函数的带宽和规律的注释
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.32
R. Stankovic, J. Astola
{"title":"Remarks on Bandwidth and Regularities in Functions on Finite Non-Abelian Groups","authors":"R. Stankovic, J. Astola","doi":"10.1109/ISMVL.2008.32","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.32","url":null,"abstract":"Sampling theorem states that under certain conditions, a signal can be reconstructed from data on a restricted area of the domain of definition of the signal model. In this context, the sampling theorem can be discussed also in the case of discrete signals to determine the minimum number of function values needed for the exact determination of a discrete function, with some additional information about the function in the spectral domain. It has been recently shown in that in the case of multiple-valued (MV) functions, the notion of bandwidth relates to the concept of essential variables. Sampling conditions convert into requirements for periodicity and regularity in the truth-vectors of multiple-valued functions. In this paper, we extend these considerations by assuming a finite non-Abelian group as the domain for a given function f to be processed.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133493154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Projective Measurement-Based Logic Synthesis of Quantum Circuits 基于投影测量的量子电路逻辑合成
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.37
M. Lukac, M. Perkowski
{"title":"Projective Measurement-Based Logic Synthesis of Quantum Circuits","authors":"M. Lukac, M. Perkowski","doi":"10.1109/ISMVL.2008.37","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.37","url":null,"abstract":"In this paper we introduce the new model for Quantum Logic Synthesis. The innovation consists in designing circuits with the measurement process together with the computing circuit. The Measurement is used as a part of the entire computational process. We demonstrate the method to synthesize quantum circuits from examples (examples are cares of the quantum truth table) such that the synthesis process converts the don't knows (minterms not given as examples) to the entangled quantum output values which are measurement dependent. We extended the logic synthesis approach to measurement-based quantum circuits synthesis from incompletely specified or completely specified function specifications.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"115 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123466741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Mature Methodology for Implementing Multi-Valued Logic in Silicon 在硅上实现多值逻辑的成熟方法
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.30
M. Nodine, C. Files
{"title":"A Mature Methodology for Implementing Multi-Valued Logic in Silicon","authors":"M. Nodine, C. Files","doi":"10.1109/ISMVL.2008.30","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.30","url":null,"abstract":"This paper gives an overview of methods proposed for implementing multi-valued logic in CMOS and then describes Intrinsity's patented Fast14reg Technology as a mature methodology for silicon implementation of multi-valued logic. To the authors' knowledge, no previous method of implementing multi-valued logic has been demonstrated with a design of the complexity of a microprocessor core. Fast14 Technology is based upon three fundamental characteristics including the use of (1) footed NMOS transistor domino logic, (2) multi-phased overlapping clocks, and (3) 1-of-N encoding of MVL signals. To provide additional opportunities for power optimization, the concepts of null value and mutex properties are introduced, presenting additional challenges for MVL representation and synthesis.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122467407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Semirigid Equivalence Relations on a Finite Set 有限集上的半刚性等价关系
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.47
M. Miyakawa, M. Pouzet, I. Rosenberg, H. Tatsumi
{"title":"Semirigid Equivalence Relations on a Finite Set","authors":"M. Miyakawa, M. Pouzet, I. Rosenberg, H. Tatsumi","doi":"10.1109/ISMVL.2008.47","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.47","url":null,"abstract":"A system R of equivalence relations on a set A (with at least 3 elements) is semirigid ;/ only the trivial opera tions (that is the projections and constant functions) preserve all members of R. To a system R of equivalence relations we associate a graph Gr. We observe that ifR is semirigid then the graph Gr is 2-connected. We show that the converse holds if all the members of R are atoms of the lattice E of equivalence relations on A. We present a notion of graphical composition of semirigid systems and show that it preserves semirigidity.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123962112","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults 基于sat的ATPG中布尔编码对路径延迟故障的影响
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.19
Stephan Eggersglüß, R. Drechsler
{"title":"On the Influence of Boolean Encodings in SAT-Based ATPG for Path Delay Faults","authors":"Stephan Eggersglüß, R. Drechsler","doi":"10.1109/ISMVL.2008.19","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.19","url":null,"abstract":"Automatic Test Pattern Generation (ATPG) is an important task to ensure that a chip functions correctly. For high speed chips, testing for dynamic fault models such as the path delay fault model becomes more and more important. While classical algorithms for ATPG reach their limit, the significance of algorithms to solve the Boolean Satisfiability (SAT) problem grows due to recent developments of powerful SAT solvers. However, ATPG is not always a purely Boolean problem. For generating robust test patterns for delay faults, multiple-valued logics are needed. To apply a (Boolean) SAT solver on a problem modeled in multiple-valued logic, a Boolean encoding has to be used. In this paper, we consider the problem of SAT-based ATPG for the robust path delay fault model where a 19- valued logic is used and provide a detailed study on the influence of the chosen Boolean encoding on the performance of test generation. Further, we show a method to identify efficient encodings and show the behavior of these encodings on ISCAS benchmarks and large industrial circuits.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125133690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram 用四元伽罗域决策图求多输出四元逻辑函数的积和表达式
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.31
Mozammel H. A. Khan, Nafisa K. Siddika, M. Perkowski
{"title":"Minimization of Quaternary Galois Field Sum of Products Expression for Multi-Output Quaternary Logic Function Using Quaternary Galois Field Decision Diagram","authors":"Mozammel H. A. Khan, Nafisa K. Siddika, M. Perkowski","doi":"10.1109/ISMVL.2008.31","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.31","url":null,"abstract":"A quaternary logic function expressed as quaternary Galois field sum of products (QGFSOP) expression can be realized as a cascade of quaternary 1-qudit, Feynman, and Toffoli gates. In this paper, we have presented a heuristic algorithm for simultaneous variable ordering and quaternary Galois field expansion selection for constructing optimal quaternary Galois field decision diagram (QGFDD). We have also shown the way of flattening the QGFDD for generating QGFSOP expression. We have written Java program to construct QGFDD for multi-output quaternary functions and provided experimental results.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125092051","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
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