Akihiro Hirosaki, M. Miura, Atsushi Matsumoto, T. Hanyu
{"title":"Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices","authors":"Akihiro Hirosaki, M. Miura, Atsushi Matsumoto, T. Hanyu","doi":"10.1109/ISMVL.2008.13","DOIUrl":null,"url":null,"abstract":"A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2008.13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A compensation method against a threshold-voltage (Vth) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the Vth variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the Vth variation.