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38th International Symposium on Multiple Valued Logic (ismvl 2008)最新文献

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Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares 不关心可逆函数的基本量子门电路的精确合成
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.42
Daniel Große, R. Wille, G. Dueck, R. Drechsler
{"title":"Exact Synthesis of Elementary Quantum Gate Circuits for Reversible Functions with Don't Cares","authors":"Daniel Große, R. Wille, G. Dueck, R. Drechsler","doi":"10.1109/ISMVL.2008.42","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.42","url":null,"abstract":"Compact realizations of reversible logic functions are of interest in the design of quantum computers. In this paper we present an exact synthesis algorithm, based on Boolean satisfiability (SAT), that finds the minimal elementary quantum gate realization for a given reversible function. Since these gates work in terms of qubits, a multi-valued encoding is proposed. Don't care conditions appear naturally in many reversible functions. Constant inputs are often required when a function is embedded into a reversible one. The proposed algorithm takes full advantage of don't care conditions and automatically sets the constant inputs to their optimal values. The effectiveness of the algorithm is shown on a set of benchmark functions.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115067110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells 基于通用文字单元的细粒度多值可重构VLSI
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.46
N. Okada, M. Kameyama
{"title":"Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells","authors":"N. Okada, M. Kameyama","doi":"10.1109/ISMVL.2008.46","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.46","url":null,"abstract":"A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit- serial reconfigurable computation is proposed. One of an arbitrary 2-variable binary logic operation, an addition and a subtraction can be executed by one cell. Also, an ntimesn-bit multiplication can be executed by 4n cells. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a very simple cell can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple- valued signaling, where superposition of serial data bits and a start signal which indicates a head of one-word is introduced.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130215977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms 最快四元线性无关变换的性质和计算算法
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.9
C. C. Lozano, B. Falkowski, T. Luba
{"title":"Properties and Computational Algorithm for Fastest Quaternary Linearly Independent Transforms","authors":"C. C. Lozano, B. Falkowski, T. Luba","doi":"10.1109/ISMVL.2008.9","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.9","url":null,"abstract":"Sixteen fastest quaternary linearly independent (FQLI) transforms are discussed in this paper. All the presented transforms can be derived using recursive equations and their inverse recursive definitions share common structure. In this paper, the fast flow graph equations and properties for the FQLI transforms are given. Based on the relationships between the spectra of the transforms, a recursive algorithm for the computation of their spectral coefficients is also proposed which reduces the total computational cost of generating their complete spectra. Experimental results for all the FQLI transforms as well as fixed polarity Reed-Muller transform over GF(4) are also given and compared in terms of the number of nonzero spectral coefficients. The comparison shows that for some quaternary functions the new FQLI transforms can give more compact representations.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"188 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133111369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics 有限值符号逻辑中命题公式的可满足性判定
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.41
V. Chepoi, N. Creignou, M. Hermann, G. Salzer
{"title":"Deciding the Satisfiability of Propositional Formulas in Finitely-Valued Signed Logics","authors":"V. Chepoi, N. Creignou, M. Hermann, G. Salzer","doi":"10.1109/ISMVL.2008.41","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.41","url":null,"abstract":"Signed logic is a way of expressing the semantics of many-valued connectives and quantifiers in a formalism that is well-suited for automated reasoning. In this paper we consider propositional, finitely-valued formulas in clausal normal form. We show that checking the satisfiability of formulas with three or more literals per clause is either NP-complete or trivial, depending on whether the intersection of all signs is empty or not. The satisfiability of bijunctive formulas, i.e., formulas with at most two literals per clause, is decidable in linear time if the signs form a Helly family, and is NP-complete otherwise. We present a polynomial-time algorithm for deciding whether a given set of signs satisfies the Helly property. Our results unify and extend previous results obtained for particular sets of signs.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132823265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
RevLib: An Online Resource for Reversible Functions and Reversible Circuits RevLib:可逆函数和可逆电路的在线资源
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.43
R. Wille, Daniel Große, Lisa Teuber, G. Dueck, R. Drechsler
{"title":"RevLib: An Online Resource for Reversible Functions and Reversible Circuits","authors":"R. Wille, Daniel Große, Lisa Teuber, G. Dueck, R. Drechsler","doi":"10.1109/ISMVL.2008.43","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.43","url":null,"abstract":"Synthesis of reversible logic has become an active research area in the last years. But many proposed algorithms are evaluated with a small set of benchmarks only. Furthermore, results are often documented only in terms of gate counts or quantum costs, rather than presenting the specific circuit. In this paper RevLib (www.revlib.org) is introduced, an online resource for reversible functions and reversible circuits. RevLib provides a large database of functions with respective circuit realizations. RevLib is designed to ease the evaluation of new methods and facilitate the comparison of results. In addition, tools are introduced to support researchers in evaluating their algorithms and documenting their results.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131138223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 461
Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators 用evmdd表示二变量初等函数及其在函数生成器中的应用
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.14
Shinobu Nagayama, Tsutomu Sasao
{"title":"Representations of Two-Variable Elementary Functions Using EVMDDs and their Applications to Function Generators","authors":"Shinobu Nagayama, Tsutomu Sasao","doi":"10.1109/ISMVL.2008.14","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.14","url":null,"abstract":"This paper proposes a method to represent two-variable elementary functions using edge-valued multi-valued decision diagrams (EVMDDs), and presents a design method and an architecture for function generators using EVMDDs. To show the compactness of EVMDDs, this paper introduces a new class of integer-valued functions, l-restricted Mp-monotone increasing functions, and derives an upper bound on the number of nodes in an edge-valued binary decision diagram (EVBDD) for the l-restricted Mp-monotone increasing function. EVBDDs represent l-restricted Mp- monotone increasing functions more compactly than MTB- DDs and BMDs when p is small. Experimental results show that all the two-variable elementary functions considered in this paper can be converted into l-restricted Mp- monotone increasing functions with p = 1 or p = 3, and can be compactly represented by EVBDDs. Since EVMDDs have shorter paths and smaller memory size than EVBDDs, EVMDDs can produce fast and compact elementary function generators.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"30 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129144087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions 混合Reed-Muller Haar变换及其在逻辑函数谱表示约简中的应用
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.8
S. Minasyan, J. Astola, K. Egiazarian, R. Stankovic
{"title":"Hybrid Reed-Muller Haar Transform and its Application in Reduction the Spectral Representations of Logic Functions","authors":"S. Minasyan, J. Astola, K. Egiazarian, R. Stankovic","doi":"10.1109/ISMVL.2008.8","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.8","url":null,"abstract":"In this paper we present a new hybrid transform based on the Kronecker product of Reed-Muller and Reed-Muller Haar transforms. The proposed transform shares attractive properties of both Reed-Muller transform and Reed-Muller Haar transform. An example of application of hybrid transform for reduction of the number of nonzero coefficients in spectra of truth vectors of switching functions is presented. The experiments show that the proposed approach, on average, reduces the number of nonzero coefficients in the spectra of benchmark functions.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129060223","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Galois Field Approach to Modelling Gene Expression Regulation 基因表达调控建模的伽罗瓦场方法
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.35
Hosam A. Aleem, F. Mavituna, D. Green
{"title":"A Galois Field Approach to Modelling Gene Expression Regulation","authors":"Hosam A. Aleem, F. Mavituna, D. Green","doi":"10.1109/ISMVL.2008.35","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.35","url":null,"abstract":"Gene expression is the process by which the cell transforms the information in the DNA to functions, often carried out by proteins. Which genes will be expressed, depends on many factors some internal to the cell and others from the environment around it. This can be considered as a logic function prescribing gene expression in response to the different conditions. Apart from continuous models, the most common formulation of such a function is using Boolean logic. This has the major drawback of restricting analysis to binary valued variable which are not always an appropriate approximation. We propose a multiple-valued logic modelling approach on a Galois field and formulate the regulatory function using the Reed-Muller expansion. Two examples are given that illustrate the application of this approach.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Encoding Max-CSP into Partial Max-SAT 将Max-CSP编码为Partial Max-SAT
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.22
Josep Argelich, Alba Cabiscol, I. Lynce, F. Manyà
{"title":"Encoding Max-CSP into Partial Max-SAT","authors":"Josep Argelich, Alba Cabiscol, I. Lynce, F. Manyà","doi":"10.1109/ISMVL.2008.22","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.22","url":null,"abstract":"We define a number of original encodings that map Max-CSP instances into Partial Max-SAT instances. Our encodings rely on the well-known direct and support encodings from CSP into SAT. Then, we report on an experimental investigation that was conducted to compare the performance profile of our encodings on random binary Max-CSP instances. Moreover, we define a new variant of the support encoding from CSP into SAT which produces fewer clauses than the standard support encoding.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115887330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Foundations of Higher Radix Numeric Computation 高等基数数值计算基础
38th International Symposium on Multiple Valued Logic (ismvl 2008) Pub Date : 2008-05-22 DOI: 10.1109/ISMVL.2008.49
D. Matula
{"title":"Foundations of Higher Radix Numeric Computation","authors":"D. Matula","doi":"10.1109/ISMVL.2008.49","DOIUrl":"https://doi.org/10.1109/ISMVL.2008.49","url":null,"abstract":"Radix arithmetic is based on radix polynomials with addition and multiplication being polynomial arithmetic. The distinguishing feature of radix polynomials is the carry operation which identifies congruent radix polynomials modulo (x - r) where the constant r is the radix. The carry operation can be employed to reduce the range of coefficients of polynomials over the integers to prescribed \"digit sets\" which may provide canonical representations or allow redundancy. We describe choices of digit sets for higher radices employed to allow more efficient hardware depending on properties of the circuitry, whether binary or multi-valued. We describe current applications of non standard digit sets in commodity microprocessors. We close with some observations on a discrete log representation of integers where the logarithmic base is a small prime.","PeriodicalId":243752,"journal":{"name":"38th International Symposium on Multiple Valued Logic (ismvl 2008)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115628755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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