Fine-Grain Multiple-Valued Reconfigurable VLSI Using Universal-Literal-Based Cells

Abstract

A fine-grain reconfigurable VLSI for various applications including arithmetic operations is developed. In the fine-grain architecture, it is important to define a cell function which leads to high utilization of a logic block and reduction of a switch block. From the point of view, a universal-literal-based multiple-valued cell suitable for bit- serial reconfigurable computation is proposed. One of an arbitrary 2-variable binary logic operation, an addition and a subtraction can be executed by one cell. Also, an ntimesn-bit multiplication can be executed by 4n cells. A series-gating differential-pair circuit is effectively employed for implementing a full-adder circuit of Sum and a universal literal circuit. Therefore, a very simple cell can be constructed using the circuit technology. Moreover, interconnection complexity can be reduced by utilizing multiple- valued signaling, where superposition of serial data bits and a start signal which indicates a head of one-word is introduced.