Design of High-Performance Quaternary Adders Based on Output-Generator Sharing

H. Shirahama, T. Hanyu
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引用次数: 38

Abstract

Simple implementations of quaternary full adders are proposed for a high-performance multi-processor which consists of many processing elements (PEs). Arbitrary quaternary functions are represented by the combination of input-value conversion and several quaternary output generations. The use of appropriate input-value conversion makes it possible to reduce the number of output generators, which improves the performance of the resulting quaternary full adders. For example, two kinds of single PEs including a quaternary full adder and two flip-flops are implemented using the proposed method and their efficiencies are demonstrated in terms of delay and power dissipation in comparison with those of a corresponding binary CMOS implementation.
基于输出-发生器共享的高性能四元加法器设计
针对由多个处理单元组成的高性能多处理器,提出了四元全加法器的简单实现方法。任意四元函数由输入值转换和若干四元输出代的组合表示。使用适当的输入值转换可以减少输出发生器的数量,从而提高所得到的四元全加法器的性能。举例来说,采用该方法实现了包括一个四元全加法器和两个触发器的两种单pe,并与相应的二进制CMOS实现相比,在延迟和功耗方面证明了它们的效率。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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