A 3/7-Level Mixed-Mode Algorithmic Analog-to-Digital Converter

Abstract

A 3/7-level mixed-mode algorithmic analog-to- digital converter (ADC) is proposed. The operation comprises six phases to obtain the 8-bit resolution. The 3-level mode is used in the first three phases for an accurate conversion, while the 7-level mode is used for the last three phases to improve the sampling speed. Transistor-level simulations assuming 0.18-mum CMOS technology with a supply voltage of 1.8 V are carried out to estimate the circuit performance. A signal-to-noise ratio of 48.1dB (ap7.7 bit) is obtained at a sampling frequency of 12.8 MHz, which is superior to the results obtained from conventional 3-level and 7-level algorithmic ADCs.