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Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference最新文献

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A mapping from sequence-pair to rectangular dissection 从序列对到矩形剖分的映射
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600346
H. Murata, K. Fujiyoshi, Tomomi Watanabe, Y. Kajitani
{"title":"A mapping from sequence-pair to rectangular dissection","authors":"H. Murata, K. Fujiyoshi, Tomomi Watanabe, Y. Kajitani","doi":"10.1109/ASPDAC.1997.600346","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600346","url":null,"abstract":"A fundamental issue in floorplanning is in how to represent candidate solutions. A representation called sequence-pair was recently proposed. Seq-pair is so general as to represent an area minimum placement, and also efficient because it does not represent any overlapping placement. However, seq-pair is not expressive enough since channels are not represented. The paper gives a mapping from seq-pair to rectangular dissection, which represents channels by line segments. Consequently, candidate arrangements of modules and channels are successfully represented with the generality and the efficiency inherited from the seq-pair.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132573161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 42
MULTI-PRIDE: a system for supporting multi-layered printed wiring board design MULTI-PRIDE:支持多层印刷线路板设计的系统
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600124
Toshimasa Watanabe
{"title":"MULTI-PRIDE: a system for supporting multi-layered printed wiring board design","authors":"Toshimasa Watanabe","doi":"10.1109/ASPDAC.1997.600124","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600124","url":null,"abstract":"The purpose of the paper is to outline MULTI-PRIDE, a system for supporting multi-layered printed wiring board design. It consists of (i) circuit bipartition, (ii) placement and routing on each outside layer, (iii) modification of wiring and compaction, and (iv) routing on inside layers.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"135 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132113573","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A high performance FIR filter dedicated to digital video transmission 专用于数字视频传输的高性能FIR滤波器
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600063
S. Morikawa, K. Okada, Sumitaka Takeuchi, I. Shirakawa
{"title":"A high performance FIR filter dedicated to digital video transmission","authors":"S. Morikawa, K. Okada, Sumitaka Takeuchi, I. Shirakawa","doi":"10.1109/ASPDAC.1997.600063","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600063","url":null,"abstract":"A digital filter is one of the fundamental elements in the digital video transmission, and a multiplier acts as the key factor that determines the operation speed and silicon area of the filter. Even though the coefficients to the filter are desired to be programmable, it is possible to change coefficients in the vertical fly-back interval of television receivers. This allows the preloadability of coefficients to the filter such that each coefficient can be treated as a constant during the filtering operation. Motivated by such functionalities, a novel multiplier together with an FIR filter architecture is described, which has been designed by means of a 0.5 /spl mu/m double metal CMOS technology.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115025874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Power consumption in CMOS combinational logic blocks at high frequencies 高频时CMOS组合逻辑块的功耗
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600117
S. Parameswaran, Hui Guo
{"title":"Power consumption in CMOS combinational logic blocks at high frequencies","authors":"S. Parameswaran, Hui Guo","doi":"10.1109/ASPDAC.1997.600117","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600117","url":null,"abstract":"A new model for estimating dynamic power dissipation in CMOS combinational circuits at differing voltages is presented. The proposed model deals with power dissipation of circuits at saturation frequencies, where the output voltage does not reach 100% of the supply voltage and the output voltage waveform is almost a triangular waveform. We show that the dynamic power consumption at saturation frequencies is only dependent on the supply voltage, and is independent of load capacitance and switching speed. This model shows that when a circuit is working in the saturation frequency range, as the frequency is increased, the performance/power ratio is increased. However, this increase in performance/power ratio is at the expense of noise margin. The model is theoretically and empirically shown to be correct. This model can be used to design a system where the differing combinational logic blocks are supplied with differing voltages. Such a system would consume lower power than if the system was supplied by a single voltage rail.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123618309","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system 基于CAD布局数据的VLSI顺序电路在CAD链接EB测试系统中的分层故障跟踪
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600173
K. Miura, K. Nakamae, H. Fujioka
{"title":"Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system","authors":"K. Miura, K. Nakamae, H. Fujioka","doi":"10.1109/ASPDAC.1997.600173","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600173","url":null,"abstract":"A previous hierarchical fault tracing method for combinational circuits which requires only CAD layout data in the CAD-linked electron beam test system is expanded as applicable to sequential circuits. The characteristics in the method remain unchanged that allow us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit in a consistent manner independently of circuit functions. The applied results of the CAD layouts of some sequential CMOS benchmark circuits show its superiority to the guided-probe method where circuit logical functions are first extracted from the CAD layout data and then the guided-probe testing is executed.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121614420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
A transformational codesign methodology 转换的协同设计方法
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600162
T.K.-Y. Cheung, G. Hellestrand, P. Kanthamanon
{"title":"A transformational codesign methodology","authors":"T.K.-Y. Cheung, G. Hellestrand, P. Kanthamanon","doi":"10.1109/ASPDAC.1997.600162","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600162","url":null,"abstract":"We present a hardware/software codesign methodology using formal transformations. The goal is to refine a given function specification of a task to an operational structure involving both hardware and software components. The refinement process is separated into two levels, the algorithmic and the structural. Within each level, refinement is accomplished by applying sequences of transformations that preserve the functionality of an initial specification. This allows various 'correct' design alternatives to be generated and their costs analyzed. At the algorithmic level, different algorithm designs are explored, each producing a computational schedule that has a different performance cost. At the structural level, different spatial structures with different resources and performance costs are explored. These costs which characterize the designs are used to assist in the hardware/software partitioning. An example is used throughout to illustrate this methodology.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130039107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
/spl plusmn/1.5 V CMOS four-quadrant multiplier / plusmn/1.5 V CMOS四象限乘法器
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600283
S.C. Li
{"title":"/spl plusmn/1.5 V CMOS four-quadrant multiplier","authors":"S.C. Li","doi":"10.1109/ASPDAC.1997.600283","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600283","url":null,"abstract":"A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified bi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of /spl plusmn/1.5 V. For a differential input voltage range up to /spl plusmn/0.8 V, this circuit has kept nonlinearity below 0.9% and total harmonic distortion less than 1%. The -3dB bandwidth of this multiplier is 15 MHz. The chip was fabricated in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.8 /spl mu/m Single-Poly-Double-Metal (SPDM) N-well process. The chip dissipates 24.4 mW and occupies 251/spl times/653 /spl mu/m/sup 2/ active area.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130878185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
CBLO: a clustering based linear ordering for netlist partitioning CBLO:用于网表分区的基于聚类的线性排序
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600056
K. Seong, C. Kyung
{"title":"CBLO: a clustering based linear ordering for netlist partitioning","authors":"K. Seong, C. Kyung","doi":"10.1109/ASPDAC.1997.600056","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600056","url":null,"abstract":"Proposes the CBLO (clustering-based linear ordering) algorithm, which consists of both global ordering and local ordering. In the global ordering, the algorithm forms clusters from n given vertices and orders the clusters. In the local ordering, the elements in each cluster are linearly ordered. The linear order thus produced is used to obtain optimal k-way partitioning based on a scaled cost objective function. Experiments with 11 benchmark circuits for k-way (2/spl les/k/spl les/10) partitioning showed that the proposed algorithm yields an average of 10.6% improvement over MELO (multiple-eigenvector linear ordering) for k-way scaled cost partitioning.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121130247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An LSI implementation of the simple serial synchronized multistage interconnection network 一种LSI实现的简单串行同步多级互连网络
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600358
Takayuki Kamei, Masashi Sasahara, H. Amano
{"title":"An LSI implementation of the simple serial synchronized multistage interconnection network","authors":"Takayuki Kamei, Masashi Sasahara, H. Amano","doi":"10.1109/ASPDAC.1997.600358","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600358","url":null,"abstract":"A high speed switch is a critical component of multiprocessors. Multistage interconnection network (MIN) has been utilized as a switch for connection processors and memory modules in multiprocessors. Unlike the crossbar, it consists of small switching elements, and provides a high bandwidth with relatively small hardware. Most of traditional MINs are blocking networks and packets are transferred in the store-and-forward manner between switching elements with bit-parallel (8-64bits) lines. Since the width of communication paths and transferred manner cause pin-limitation problems and complicated structure, the high density implementation and high speed clock is not utilized. In order to solve these problems, we implemented the SSS-PBSF chip. This switch uses the PBSF connection structure which can obtain a higher bandwidth than that of crossbar with connecting banyan networks in a 3D direction. A simple serial synchronized (SSS) style control mechanism is adopted both for high speed operation and solving the pin-limitation problem.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127056558","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Adaptive models for input data compaction for power simulators 功率模拟器输入数据压缩的自适应模型
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600263
R. Marculescu, Diana Marculescu, Massoud Pedram
{"title":"Adaptive models for input data compaction for power simulators","authors":"R. Marculescu, Diana Marculescu, Massoud Pedram","doi":"10.1109/ASPDAC.1997.600263","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600263","url":null,"abstract":"Presents an effective and robust technique for compacting a large sequence of input vectors into a much smaller input sequence so as to reduce the circuit/gate-level simulation time by orders of magnitude and maintain the accuracy of the power estimates. In particular, this paper introduces and characterizes a family of dynamic Markov trees that can model complex the spatiotemporal correlations which occur during power estimation in both combinational and sequential circuits. As the results demonstrate, large compaction ratios of 1-2 orders of magnitude can be obtained without a significant loss (less than 5% on average) in the accuracy of the power estimates.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125502206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 30
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