/ plusmn/1.5 V CMOS四象限乘法器

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI:10.1109/ASPDAC.1997.600283

S.C. Li

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引用次数: 0

摘要

提出了一种采用改进的双向调节级联码(RGC)结构，在三极管区使用两个NMOS的低压CMOS四象限模拟乘法器。该电路可以在/spl plusmn/1.5 V的电源电压下工作。对于高达/spl plusmn/0.8 V的差分输入电压范围，该电路将非线性保持在0.9%以下，总谐波失真小于1%。该乘法器的-3dB带宽为15mhz。该芯片采用台湾积电(TSMC) 0.8 /spl mu/m单多双金属(SPDM) n阱工艺制造。芯片功耗24.4 mW，占用251/spl倍/653 /spl亩/sup 2/有源面积。

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/spl plusmn/1.5 V CMOS four-quadrant multiplier

A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified bi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of /spl plusmn/1.5 V. For a differential input voltage range up to /spl plusmn/0.8 V, this circuit has kept nonlinearity below 0.9% and total harmonic distortion less than 1%. The -3dB bandwidth of this multiplier is 15 MHz. The chip was fabricated in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.8 /spl mu/m Single-Poly-Double-Metal (SPDM) N-well process. The chip dissipates 24.4 mW and occupies 251/spl times/653 /spl mu/m/sup 2/ active area.

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Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

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