发布求助
文献互助 智能选刊 最新文献

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference最新文献

筛选
英文 中文
Design driven partitioning 设计驱动分区
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600057
D. Behrens, E. Barke, Robert Tolkiehn
{"title":"Design driven partitioning","authors":"D. Behrens, E. Barke, Robert Tolkiehn","doi":"10.1109/ASPDAC.1997.600057","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600057","url":null,"abstract":"A new approach for partitioning VLSI digital integrated circuits is presented. In contrast to known approaches, which use only topological information, the presented method also exploits specific information about design modules and higher-level design structure. Based on this knowledge, the design-driven procedure creates a cluster structure that incorporates the inherent design relationships (e.g. signal flow, logic blocks) in the best way possible. Followed by standard iterative improvement algorithms, partitions are produced that outperform many partitioning approaches published before. Because of its linear time complexity, the presented clustering strategy is able to handle very large designs. Due to its modular structure, it can be easily extended to incorporate special design features or target architectures such as emulation systems.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128473847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Super low power 8-bit CPU with pass-transistor logic 超低功耗8位CPU与通管逻辑
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600352
K. Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi
{"title":"Super low power 8-bit CPU with pass-transistor logic","authors":"K. Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi","doi":"10.1109/ASPDAC.1997.600352","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600352","url":null,"abstract":"A very low power 8-bit CPU core has been designed based on an original pass-transistor logic family, the SPL (single-rail pass-transistor logic) and SPHL (single-rail pass-transistor and holders logic). The instruction set and external timings are compatible with the Zilog Z80. The average supply current is 740 /spl mu/A at 3 V with a 10 MHz-clock, equivalent to 26% of that of the commercial CMOS Z80 CPU cores using the same design rules.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129658349","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
A note on the relationship between signal probability and switching activity 关于信号概率与开关活动之间关系的说明
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600070
Qing Wu, Massoud Pedram, Xunwei Wu
{"title":"A note on the relationship between signal probability and switching activity","authors":"Qing Wu, Massoud Pedram, Xunwei Wu","doi":"10.1109/ASPDAC.1997.600070","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600070","url":null,"abstract":"In current probability calculation algorithms for power estimation, switching activity E/sub SW/ of a node is calculated from its signal probability p by the following simple relation: E/sub SW/=2p(1-p). It is generally understood that this simple relationship holds under the temporal independence assumption for the node. This paper however shows that the above equation also gives the expected value of the transition activity in any sequence that satisfies the given signal probability (averaged over all such sequences). Therefore, this equation can be used to calculate the switching activity under more general conditions than previously thought.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114803969","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Efficient synthesis of AND/XOR networks AND/XOR网络的高效合成
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600329
Y. Ye, K. Roy
{"title":"Efficient synthesis of AND/XOR networks","authors":"Y. Ye, K. Roy","doi":"10.1109/ASPDAC.1997.600329","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600329","url":null,"abstract":"A new graph-based synthesis method for general Exclusive Sum-of-Product forms (ESOP) is presented in this paper. Previous research has largely concentrated on a class of ESOP's, the Canonical Restricted Fixed/Mixed Polarity Reed-Muller form, also known as Generalized Reed-Muller (GRM) form. However, for many functions, the minimum GRM can be much worse than the ESOP. We have defined a Shared Multiple Rooted XOR-based Decomposition Diagram (XORDD) to represent functions with multiple outputs. By iteratively applying transformations and reductions, we obtain a compact XORDD which gives a minimized ESOP. Our method can synthesize larger circuits than previously possible. The compact ESOP representation provides a form that is easier to synthesize for XOR heavy multilevel circuit, such as arithmetic functions. The method successfully minimized large functions with multiple outputs. Results are also compared to the minimized SOP's obtained from ESPRESSO. Experimental results show that for many circuits ESOP's have considerably more compact form than SOP's.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"92-D 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128005141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Bit-serial pipeline synthesis and layout for large-scale configurable systems 大规模可配置系统的位串行管道综合与布局
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600298
T. Isshiki, W. Dai, H. Kunieda
{"title":"Bit-serial pipeline synthesis and layout for large-scale configurable systems","authors":"T. Isshiki, W. Dai, H. Kunieda","doi":"10.1109/ASPDAC.1997.600298","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600298","url":null,"abstract":"In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale configurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115824384","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Analysis and design of multiple-bit high-order /spl Sigma/-/spl Delta/ modulator 多位高阶/spl Sigma/-/spl Delta/调制器的分析与设计
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600279
Hao-Chiao Hong, Bin-Hong Lin, Cheng-Wen Wu
{"title":"Analysis and design of multiple-bit high-order /spl Sigma/-/spl Delta/ modulator","authors":"Hao-Chiao Hong, Bin-Hong Lin, Cheng-Wen Wu","doi":"10.1109/ASPDAC.1997.600279","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600279","url":null,"abstract":"The high-order /spl Sigma/-/spl Delta/ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order /spl Sigma/-/spl Delta/ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130452639","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs 基于路径长度约束的传输处理fpga同步布局和全局路由算法
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600338
N. Togawa, M. Sato, T. Ohtsuki
{"title":"A simultaneous placement and global routing algorithm with path length constraints for transport-processing FPGAs","authors":"N. Togawa, M. Sato, T. Ohtsuki","doi":"10.1109/ASPDAC.1997.600338","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600338","url":null,"abstract":"In the layout design of transport-processing FPGAs, it is not only required that routing congestion be kept small but also that circuits implemented on them should operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs, whose objective is to minimize the routing congestion, and proposes a new algorithm, in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on the hierarchical bipartitioning of the layout regions and LUT (lookup table) sets that are to be placed. Each bipartitioning procedure consists of three phases: (1) estimation of path lengths, (2) bipartitioning of a set of terminals, and (3) bipartitioning of a set of LUTs. After searching the paths with tighter path length constraints by estimating the path lengths in (1), phases (2) and (3) are executed so that their path lengths are reduced with higher priority, and thus path length constraints are not violated. The algorithm has been implemented and applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm resolves path length constraints for 11 out of 13 circuits, though it increases the routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and reduces the circuit delay by an average of 23%.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134444360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An optimal scheduling method for parallel processing system of array architecture 阵列结构并行处理系统的最优调度方法
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600300
K. Ito, T. Iwata, H. Kunieda
{"title":"An optimal scheduling method for parallel processing system of array architecture","authors":"K. Ito, T. Iwata, H. Kunieda","doi":"10.1109/ASPDAC.1997.600300","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600300","url":null,"abstract":"In high-level synthesis for digital signal processing systems of array structured architecture, one of the most important procedures is the scheduling. By taking into account the allocation of operations to processors, it is mandatory to take into account the communication time between processors. In this paper we propose a scheduling method which derives an optimal schedule achieving the minimum iteration period and latency for a given signal processing algorithm on the specified processor array. The scheduling problem is modeled as an integer linear programming and solved by an ILP solver. Furthermore, we improve the scheduling method so that it can be applied to large scale signal processing algorithms without degrading the schedule optimality.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131112748","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Concurrent cell generation and mapping for CMOS logic circuits CMOS逻辑电路的并发单元生成和映射
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600134
M. Kanecko, Jialin Tian
{"title":"Concurrent cell generation and mapping for CMOS logic circuits","authors":"M. Kanecko, Jialin Tian","doi":"10.1109/ASPDAC.1997.600134","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600134","url":null,"abstract":"The conventional technology mapping method is selecting cells from a limited standard library, and the performance of the resultant circuit deeply depends on the characteristics of the library. To realize detailed optimization not limited by an instance of cell library and to reduce the maintenance cost of standard cell libraries, a novel paradigm for technology mapping, in which cell generation and mapping can be executed concurrently, is considered. This paper shows an outline of a concurrent cell generation and mapping strategy, and proposes a method to map an input Boolean network into CMOS transistor network. The transduction in transistor level is introduced for cell generation and the Dynamic Programming is utilized for cell assignment.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115571160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Statistical design of macro-models for RT-level power evaluation rt水平功率评价宏观模型的统计设计
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600325
Qing Wu, Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram
{"title":"Statistical design of macro-models for RT-level power evaluation","authors":"Qing Wu, Chih-Shun Ding, Cheng-Ta Hsieh, Massoud Pedram","doi":"10.1109/ASPDAC.1997.600325","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600325","url":null,"abstract":"This paper introduces the notion of cycle-accurate macro-models for RT-level power evaluation. These macro-models provide us with the capability to estimate the circuit power dissipation cycle by cycle at RT-level without the need to invoke low level simulations. The statistical framework allows us to compute the error interval for the predicted value from the user specified confidence level. The proposed macro-model generation strategy has been applied to a number of RT-level blocks and detailed results and comparisons are provided.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124222753","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信