大规模可配置系统的位串行管道综合与布局

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI:10.1109/ASPDAC.1997.600298

T. Isshiki, W. Dai, H. Kunieda

{"title":"大规模可配置系统的位串行管道综合与布局","authors":"T. Isshiki, W. Dai, H. Kunieda","doi":"10.1109/ASPDAC.1997.600298","DOIUrl":null,"url":null,"abstract":"In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale configurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Bit-serial pipeline synthesis and layout for large-scale configurable systems\",\"authors\":\"T. Isshiki, W. Dai, H. Kunieda\",\"doi\":\"10.1109/ASPDAC.1997.600298\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale configurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner.\",\"PeriodicalId\":242487,\"journal\":{\"name\":\"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference\",\"volume\":\"52 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-01-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1997.600298\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1997.600298","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

在本文中，我们提出了我们的数据路径合成和布局工具，这些工具针对具有高达数百万门的逻辑容量的大规模可配置系统，其中包括使用c++的简单设计入口，用于基于sram的fpga的定制位串行电路库，位串行流水线电路发生器和电路分区器。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Bit-serial pipeline synthesis and layout for large-scale configurable systems

In this paper, we present our datapath synthesis and layout tools which are targeted toward large-scale configurable systems with the logic capacity of up to millions of gates which consists of an easy design entry using C++, customized bit-serial circuit library for SRAM-based FPGAs, bit-serial pipeline circuit generator, and a circuit partitioner.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

自引率

0.00%

发文量