多位高阶/spl Sigma/-/spl Delta/调制器的分析与设计

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI:10.1109/ASPDAC.1997.600279

Hao-Chiao Hong, Bin-Hong Lin, Cheng-Wen Wu

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引用次数: 2

摘要

高阶/spl Sigma/-/spl Delta/调制器是高带宽、高分辨率A/D转换的合适方法。然而，有限运算放大器增益和电容失配等非理想效应对其在低过采样比下的性能有很大影响。为了在不可避免的非理想影响下获得更高的性能，我们基于CIQE高阶/spl Sigma/-/spl Delta/架构探索了几种多比特方案，以消除非理想劣化。并通过大量的仿真验证了这些多比特方案的设计规则。

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Analysis and design of multiple-bit high-order /spl Sigma/-/spl Delta/ modulator

The high-order /spl Sigma/-/spl Delta/ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order /spl Sigma/-/spl Delta/ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.

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Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

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