超低功耗8位CPU与通管逻辑

Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI:10.1109/ASPDAC.1997.600352

K. Taki, Bu-Yeol Lee, Hideki Tanaka, Kenzo Konishi

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引用次数: 6

摘要

一个非常低功耗的8位CPU核心已经设计基于原始的通型晶体管逻辑家族，SPL(单轨通型晶体管逻辑)和SPHL(单轨通型晶体管和持位逻辑)。指令集和外部时序与Zilog Z80兼容。在3v和10mhz时钟下，平均电源电流为740 /spl mu/A，相当于使用相同设计规则的商用CMOS Z80 CPU内核的26%。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Super low power 8-bit CPU with pass-transistor logic

A very low power 8-bit CPU core has been designed based on an original pass-transistor logic family, the SPL (single-rail pass-transistor logic) and SPHL (single-rail pass-transistor and holders logic). The instruction set and external timings are compatible with the Zilog Z80. The average supply current is 740 /spl mu/A at 3 V with a 10 MHz-clock, equivalent to 26% of that of the commercial CMOS Z80 CPU cores using the same design rules.

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Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference

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