Analysis and design of multiple-bit high-order /spl Sigma/-/spl Delta/ modulator

Abstract

The high-order /spl Sigma/-/spl Delta/ modulator is an appropriate approach for high-bandwidth, high-resolution A/D conversion. However, non-ideal effects such as the finite op-amp gain and the capacitor mismatch have great impacts on its performance at a low oversampling ratio. To achieve greater performance under the inevitable non-ideal effects, we explore several multiple-bit schemes, based on our CIQE high-order /spl Sigma/-/spl Delta/ architecture, to remove the non-ideal deterioration. Design rules of these multiple-bit schemes are developed and verified by extensive simulations.