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Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference最新文献

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A new approach for an AHDL based on system semantics 一种基于系统语义的AHDL新方法
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600120
Y. Bourai, N. Izeboudjen, Yacine Bouhabel, A. Tafat
{"title":"A new approach for an AHDL based on system semantics","authors":"Y. Bourai, N. Izeboudjen, Yacine Bouhabel, A. Tafat","doi":"10.1109/ASPDAC.1997.600120","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600120","url":null,"abstract":"A new approach to Analog Hardware Design Languages (AHDL) is presented. This is based on the system semantics principle. This principle allows one to define a language that provides a unified syntax to describe the different aspects of an Op-Amp. This is possible because the basic components of an Op-Amp are adirectional systems. These components are described by combinators. A set of semantic functions are applied to these combinators to give them meaning.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114863752","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Choosing a digital simulator 选择数字模拟器
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600211
J. Hillawi
{"title":"Choosing a digital simulator","authors":"J. Hillawi","doi":"10.1109/ASPDAC.1997.600211","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600211","url":null,"abstract":"This paper summarises the second in a series of benchmarking efforts conducted by DA Solutions between August 1995 and April 1996, for VHDL and Verilog simulators. The paper discusses the methodology used and the results of an independent public benchmark for leading VHDL and Verilog simulators, for RTL, Gate, VITAL and Co-simulations products. The paper also makes performance comparisons between VHDL and Verilog technologies and between PC and UNIX solutions.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114913413","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An improved objective for cell placement 改进的细胞放置目标
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600155
Yu-Wen Tsay, Hsiao-Pin Su, Y. Lin
{"title":"An improved objective for cell placement","authors":"Yu-Wen Tsay, Hsiao-Pin Su, Y. Lin","doi":"10.1109/ASPDAC.1997.600155","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600155","url":null,"abstract":"To estimate the wiring area needed by the router to connect a signal net, most placement tools measure one half of the perimeter of the minimum rectangle enclosing all terminals of the net. In the past, this approach is reasonable because the half-perimeter value correlates well with the wiring area. As we are entering the deep-submicron era, the approach is no longer appropriate because the wiring delay must be characterized based on a distributed-RC model, in which not only the wiring area but also the wiring topology affects the wiring delay. In this paper, we show that the half-perimeter metric does not correlate well with the wiring delay under the distributed-RC model. We show that the radius of a net estimates the wiring delay more accurately than the half-perimeter metric does. We expand the acceptance criteria of a simulated annealing based placement tool to include moves that do not improve on the wiring length but do reduce the radius. Over all, for a set of benchmark circuits the critical path delays are improved up to 15%.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124729306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
The EUROPRACTICE MPC service EUROPRACTICE MPC服务
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600205
C. Das
{"title":"The EUROPRACTICE MPC service","authors":"C. Das","doi":"10.1109/ASPDAC.1997.600205","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600205","url":null,"abstract":"IMEC has been involved in MPC services for universities and industry since 1984. In the beginning these services were set up to support the local educational programme. Later on in 1989, IMEC was coordinator of the European wide MPC services in the EC funded project EUROCHIP. Today since October 1995, IMEC has been coordinator of the IC Manufacturing Service in the EC funded project EUROPRACTICE. The paper discusses the EUROPRACTICE project, an ESPRIT initiative in the field of European microelectronics. EUROPRACTICE will concentrate primarily on three microelectronics-based technologies: application specific integrated circuits (ASICs), multi-chip modules (MCMs) and microsystems. The paper considers the EUROPRACTICE MPC service in detail.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129316525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
EMC-adequate design of printed circuit boards as a part of the system development 适当的印刷电路板emc设计作为系统开发的一部分
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600122
W. Jophn
{"title":"EMC-adequate design of printed circuit boards as a part of the system development","authors":"W. Jophn","doi":"10.1109/ASPDAC.1997.600122","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600122","url":null,"abstract":"The EMC-adequate design of microelectronic systems includes all actions intended to eliminate electromagnetic interference in electronic systems. Challenges faced in the microelectronic area include growing system complexity, higher operating speed, denser design at all levels of integration (chip, printed circuit board, MCM and system). Growing complexity, denser design and higher speed all lead to a substantial increase in EMC problems and design time. EMC is not commonly accepted in microelectronic design. Microelectronic designers have the opinion that EMC has to do with electrical and electronic systems and mandatory product regulations instead of requirements to the integrated circuit they are designing, In this contribution a concept for an EMC-adequate design of electronic systems will be introduced. This concept is based on a generalized development process to integrate EMC-constraints into system design. A prototype of an environment to analyse signal integrity effects on PCB based on a workflow oriented integration approach will be introduced. Based on this approach the generation of user specific design and analysis environments including various set of EMC-tools is possible,.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114210750","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications ChipEst-FPGA:用于高级应用的基于查找表的fpga的芯片级面积和时序估计工具
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600292
Min Xu, F. Kurdahi
{"title":"ChipEst-FPGA: a tool for chip level area and timing estimation of lookup table based FPGAs for high level applications","authors":"Min Xu, F. Kurdahi","doi":"10.1109/ASPDAC.1997.600292","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600292","url":null,"abstract":"The importance of efficient area and timing estimation techniques for hierarchical design methodology is well-established in High-Level Synthesis (HLS), since the estimation allows more realistic exploration of the design space, and hierarchical design methodology matches well with HLS paradigm. In this paper, we present ChipEst-FPGA, a chip level estimator for designs implemented using a hierarchical design methodology for Lookup Table Based FPGAs. In FPGAs, the wire delay may contribute to a significant portion of the overall design delay. ChipEst-FPGA uses a realistic model which takes the component area/delay as well as wiring effects into account. We tested our ChipEst-FPGA on several benchmarks and the results show that we can get accurate area and timing estimates efficiently.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115275446","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface 基于HDL模拟器和操作系统接口的微处理器软硬件协同仿真环境设计
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600243
Yoshiyuki Ito, Yuichi Nakamura
{"title":"A hardware/software co-simulation environment for micro-processor design with HDL simulator and OS interface","authors":"Yoshiyuki Ito, Yuichi Nakamura","doi":"10.1109/ASPDAC.1997.600243","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600243","url":null,"abstract":"Proposes a hardware/software co-simulation environment using an RTL (register transfer level) simulator with a software language interface. The proposed simulation environment introduces the \"operating system interface\" (OSIF), which invokes system calls in the OS on the simulation platform to execute application software. The OSIF consists of data adaption facility and function correspondence management allowing it to cooperate with the OS of the simulation platform. We show the results of experiments with an R3000-compatible processor model. This environment verified our processor model with SPEC benchmarks that require various OS services. For example, with the Lisp interpreter program li, our detailed RTL description for the core part of R3000 was simulated only within 20 hours on a 109 MIPS workstation.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121706412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Reducing the complexity of path classification by reconvergence analysis 通过再收敛分析降低路径分类的复杂度
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600269
P. Tafertshofer, A. Ganz, M. Henftling
{"title":"Reducing the complexity of path classification by reconvergence analysis","authors":"P. Tafertshofer, A. Ganz, M. Henftling","doi":"10.1109/ASPDAC.1997.600269","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600269","url":null,"abstract":"We present a new and efficient method for path classification, i.e. for determining the set of functional unsensitizable or robust dependent paths, in combinational circuits. In a pre-processing step, the new method computes a minimal set of reconvergence regions that need to be considered for path classification. Functional sensitization is only performed for path segments contained in these regions. Thus, the complexity for path classification can be reduced from the total number of paths in the circuit to the number of paths contained in the minimal set of reconvergence regions.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"112 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121511512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Fuzzy-based circuit partitioning in built-in current testing 内置电流测试中基于模糊的电路划分
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600267
W. Tseng, Kuochen Wang
{"title":"Fuzzy-based circuit partitioning in built-in current testing","authors":"W. Tseng, Kuochen Wang","doi":"10.1109/ASPDAC.1997.600267","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600267","url":null,"abstract":"Partitioning a digital circuit into modules before implementing it on a single chip is key to balancing between the test cost and test correctness of built-in current testing (BICT). Most partitioning methods use statistical analysis to find the threshold value and then to determine the size of a module. These methods are rigid and inflexible, since IDDQ testing requires the measurement of an analog quantity rather than a digital signal. In this paper, we propose a fuzzy-based approach which provides a soft threshold to determine the module size for BICT partitioning. Evaluation results show that our design approach indeed provides a feasible way to exploit the design space of BICT partitioning.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125693776","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements 用线性边界元并行计算三维寄生电阻和寄生电容
Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference Pub Date : 1997-01-28 DOI: 10.1109/ASPDAC.1997.600200
Wenming Zhou, Zeyi Wang, Lan Rao
{"title":"Parallel calculation of 3-D parasitic resistance and capacitance with linear boundary elements","authors":"Wenming Zhou, Zeyi Wang, Lan Rao","doi":"10.1109/ASPDAC.1997.600200","DOIUrl":"https://doi.org/10.1109/ASPDAC.1997.600200","url":null,"abstract":"Because of the widespread application of deep sub-micron and multilayer routing techniques, the interconnection parasitic influence has more and more effect on the performance of VLSI circuits. Parallel direct boundary element calculation of three-dimensional (3-D) resistance and capacitance is an important method for fast extraction. In this paper, a parallel algorithm to implement linear boundary element calculation using PVM (Parallel Virtual Machine, distributed calculating software) is introduced. The hierarchical calculation scheme of the setup and solution processes of linear equations is discussed. At the end, the performance and workload balance of the algorithm are analyzed.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122816461","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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