{"title":"选择数字模拟器","authors":"J. Hillawi","doi":"10.1109/ASPDAC.1997.600211","DOIUrl":null,"url":null,"abstract":"This paper summarises the second in a series of benchmarking efforts conducted by DA Solutions between August 1995 and April 1996, for VHDL and Verilog simulators. The paper discusses the methodology used and the results of an independent public benchmark for leading VHDL and Verilog simulators, for RTL, Gate, VITAL and Co-simulations products. The paper also makes performance comparisons between VHDL and Verilog technologies and between PC and UNIX solutions.","PeriodicalId":242487,"journal":{"name":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-01-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Choosing a digital simulator\",\"authors\":\"J. Hillawi\",\"doi\":\"10.1109/ASPDAC.1997.600211\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper summarises the second in a series of benchmarking efforts conducted by DA Solutions between August 1995 and April 1996, for VHDL and Verilog simulators. The paper discusses the methodology used and the results of an independent public benchmark for leading VHDL and Verilog simulators, for RTL, Gate, VITAL and Co-simulations products. The paper also makes performance comparisons between VHDL and Verilog technologies and between PC and UNIX solutions.\",\"PeriodicalId\":242487,\"journal\":{\"name\":\"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference\",\"volume\":\"8 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-01-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASPDAC.1997.600211\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of ASP-DAC '97: Asia and South Pacific Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASPDAC.1997.600211","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper summarises the second in a series of benchmarking efforts conducted by DA Solutions between August 1995 and April 1996, for VHDL and Verilog simulators. The paper discusses the methodology used and the results of an independent public benchmark for leading VHDL and Verilog simulators, for RTL, Gate, VITAL and Co-simulations products. The paper also makes performance comparisons between VHDL and Verilog technologies and between PC and UNIX solutions.