/spl plusmn/1.5 V CMOS four-quadrant multiplier

Abstract

A low-voltage CMOS four-quadrant analogue multiplier using two NMOS operated in the triode region with modified bi-directional regulated cascode (RGC) structure is presented. The circuit can operate from a supply voltage of /spl plusmn/1.5 V. For a differential input voltage range up to /spl plusmn/0.8 V, this circuit has kept nonlinearity below 0.9% and total harmonic distortion less than 1%. The -3dB bandwidth of this multiplier is 15 MHz. The chip was fabricated in Taiwan Semiconductor Manufacturing Corporation (TSMC) 0.8 /spl mu/m Single-Poly-Double-Metal (SPDM) N-well process. The chip dissipates 24.4 mW and occupies 251/spl times/653 /spl mu/m/sup 2/ active area.