Hierarchical fault tracing for VLSI sequential circuits from CAD layout data in the CAD-linked EB test system

Abstract

A previous hierarchical fault tracing method for combinational circuits which requires only CAD layout data in the CAD-linked electron beam test system is expanded as applicable to sequential circuits. The characteristics in the method remain unchanged that allow us to trace a fault hierarchically from the top level cell to the lowest primitive cell and from the primitive cell to the transistor-level circuit in a consistent manner independently of circuit functions. The applied results of the CAD layouts of some sequential CMOS benchmark circuits show its superiority to the guided-probe method where circuit logical functions are first extracted from the CAD layout data and then the guided-probe testing is executed.