2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第10页

Large Forests and Where to “Partially” Fit Them 大森林和哪里“部分”适合他们

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712534

Andrea Damiani, Emanuele Del Sozzo, M. Santambrogio

引用次数: 3

Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS 基于HLS的自动行为输入语言转换提高硬件加速器的质量

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712582

M. I. Rashid, Benjamin Carrión Schäfer

{"title":"Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS","authors":"M. I. Rashid, Benjamin Carrión Schäfer","doi":"10.1109/asp-dac52403.2022.9712582","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712582","url":null,"abstract":"High-Level Synthesis (HLS) is now part of most standard VLSI design flows and there are numerous commercial HLS tools available. One persistent problem of HLS is that the quality of results (QoR) still heavily depends on minor things like how the code is written. One additional observation that we have made in this work is that the input language used for the same HLS tool affects the QoR. HLS tools (commercial and academic) are built in a modular way which typically include a separate front-end (parser) for each input language supported. These front-ends parse the untimed behavioral descriptions, perform numerous technology independent optimizations and output a common intermediate representations (IR) for all different input languages supported. These optimizations also heavily depend on the synthesis directives set by the designer. These directives in the form of pragmas allow to control how to synthesize arrays (register or RAM), loops (unroll or not or pipeline) and functions (inline or not). We have observed that two functional equivalent behavioral descriptions with the same set of synthesis directives often lead to circuits with different QoR for the same HLS tool. Thus, automated approaches are needed to help designers to generate the best possible circuit independently of the input language used. To address this, in this work we propose using Graph Convolutional Networks (GCN) to determine the best language for a given new behavioral description and present an automated language converter for HLS.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

A Graph Neural Network Method for Fast ECO Leakage Power Optimization 基于图神经网络的ECO泄漏功率快速优化

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712486

Kai Wang, Peng Cao

{"title":"A Graph Neural Network Method for Fast ECO Leakage Power Optimization","authors":"Kai Wang, Peng Cao","doi":"10.1109/ASP-DAC52403.2022.9712486","DOIUrl":"https://doi.org/10.1109/ASP-DAC52403.2022.9712486","url":null,"abstract":"In modern design, engineering change order (ECO) is often utilized to perform power optimization including gate-sizing and Vth-assignments, which is efficient but highly timing consuming. Many graph neural network (GNN) based methods are recently proposed for fast and accurate ECO power optimization by considering neighbors' information. Nonetheless, these works fail to learn high-quality node representations on directed graph since they treat all neighbors uniformly when gathering their information and lack local topology information from neighbors one or two-hop away. In this paper, we introduce a directed GNN based method which learns information from different neighbors respectively and contains rich local topology information, which was validated by the Opencores and IWLS 2005 benchmarks with TSMC 28nm technology. Experimental results show that our approach outperforms prior GNN based methods with at least 7.8% and 7.6% prediction accuracy improvement for seen and unseen designs respectively as well as 8.3% to 29.0% leakage optimization improvement. Compared with commercial EDA tool PrimeTime, the proposed framework achieves similar power optimization results with up to 12X runtime improvement.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125946235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Data Leakage through Self-Terminated Write Schemes in Memristive Caches 记忆缓存中自终止写机制导致的数据泄漏

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712492

Jonas Krautter, M. Mayahinia, Dennis R. E. Gnad, M. Tahoori

引用次数: 1

Improving the Robustness of Microfluidic Networks 提高微流体网络的鲁棒性

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712527

G. Fink, Philipp Ebner, Sudip Poddar, R. Wille, J. Kepler

{"title":"Improving the Robustness of Microfluidic Networks","authors":"G. Fink, Philipp Ebner, Sudip Poddar, R. Wille, J. Kepler","doi":"10.1109/asp-dac52403.2022.9712527","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712527","url":null,"abstract":"Microfluidic devices, often in the form of Lab-on-a-Chip (LoCs), are successfully utilized in many domains such as medicine, chemistry, biology, etc. However, neither the fabrication process nor the respectively used materials are perfect and, thus, defects are frequently induced into the actual physical realization of the device. This is especially critical for sensitive devices such as droplet-based microfluidic networks that are able to route droplets inside channels along different paths by only exploiting passive hydrodynamic effects. However, these passive hydrodynamic effects are very sensitive and already slight changes of parameters (e.g., in the channel width) can alter the behavior, even in such a way that the intended functionality of the network breaks. Hence, it is important that microfluidic networks become robust against such defects in order to prevent erroneous behavior. But considering such defects during the design process is a non-trivial task and, therefore, designers mostly neglected such considerations thus far. To overcome this problem, we propose a robustness improvement process that allows to optimize an initial design in such a way that it becomes more robust against defects (while still retaining the original behavior of the initial design). To this end, we first utilize a metric to compare the robustness of different designs and, afterwards, discuss methods that aim to improve the robustness. The metric and methods are demonstrated by an example and also tested on several networks to show the validity of the robustness improvement process.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129879657","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

On the Viability of Decision Trees for Learning Models of Systems 系统学习模型决策树的可行性研究

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712579

Swantje Plambeck, Lutz Schammer, Görschwin Fey

引用次数: 4

Transient Adjoint DAE Sensitivities: a Complete, Rigorous, and Numerically Accurate Formulation 瞬态伴随DAE灵敏度:一个完整的，严格的，数值精确的公式

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712537

Naomi Sagan, J. Roychowdhury

引用次数: 0

An Accuracy Reconfigurable Vector Accelerator Based on Approximate Logarithmic Multipliers 基于近似对数乘法器的精度可重构矢量加速器

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712504

Lingxia Hou, Yutaka Masuda, T. Ishihara

引用次数: 2

Computation-in-Memory Accelerators for Secure Graph Database: Opportunities and Challenges 面向安全图形数据库的内存计算加速器:机遇与挑战

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712502

Md Tanvir Arafin

引用次数: 0

SYNTHNET: A High-throughput yet Energy-efficient Combinational Logic Neural Network SYNTHNET:一种高通量、高能效的组合逻辑神经网络

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712554

Tianen Chen, Taylor Kemp, Younghyun Kim

{"title":"SYNTHNET: A High-throughput yet Energy-efficient Combinational Logic Neural Network","authors":"Tianen Chen, Taylor Kemp, Younghyun Kim","doi":"10.1109/asp-dac52403.2022.9712554","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712554","url":null,"abstract":"In combinational logic neural networks (CLNNs), neurons are realized as combinational logic circuits or look-up tables (LUTs). They make make extremely low-latency inference possible by performing the computation with pure hardware without loading weights from the memory. The high throughput, however, is powered by massively parallel logic circuits or LUTs and hence comes with high area occupancy and high energy consumption. We present SYNTHNET, a novel CLNN design method that effectively identifies and keeps only the sublogics that play a critical role in the accuracy and remove those which do not contribute to improving the accuracy. It captures the abundant redundancy in NNs that can be exploited only in CLNNs, and thereby dramatically reduces the energy consumption of CLNNs with minimal accuracy degradation. We prove the efficacy of SYNTHNET on the CIFAR-10 dataset, maintaining a competitive accuracy while successfully replacing layers of a VGG-style network which traditionally uses memory-based floating point operations with combinational logic. Experimental results suggest our design can reduce energy-consumption of CLNNs more than 90% compared to the state-of-the-art design.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130780403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1