2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)最新文献_第9页

Efficient Preparation of Cyclic Quantum States 循环量子态的高效制备

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712522

Fereshte Mozafari, Yuxiang Yang, G. Micheli

引用次数: 1

NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric Chips nr -路由器:非规则电极路由与最佳引脚选择电润湿介质芯片

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712567

Hsin-Chuan Huang, Chia-Chun Liang, Qining Wang, Xing Huang, Tsung-Yi Ho, Chang-Jin Kim

{"title":"NR-Router: Non-Regular Electrode Routing with Optimal Pin Selection for Electrowetting-on-Dielectric Chips","authors":"Hsin-Chuan Huang, Chia-Chun Liang, Qining Wang, Xing Huang, Tsung-Yi Ho, Chang-Jin Kim","doi":"10.1109/asp-dac52403.2022.9712567","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712567","url":null,"abstract":"With the advances in microfluidics, electrowetting-on-dielectric (EWOD) chips have widely been applied to various laboratory procedures. Glass-based EWOD chips with non-regular electrodes are proposed, which allow more reliable droplet operations and facilitating integration of optical sensors for many biochemical applications. Besides, non-regular electrode designs (e.g., interdigitated electrodes) are utilized in EWOD chips to precisely control droplet volume, and electrodes with a specific shape become necessary for certain applications. However, due to the technical barriers of fabricating multi-layer interconnection on the glass substrate (e.g., unreliable process and high cost), both control electrodes and wires are fabri-cated with a single-layer configuration, which poses significant challenges to pin selection for non-regular electrodes under the limited routing resource. In this paper, we propose a minimum cost flow-based routing algorithm called NR-Router that features efficient and robust routing for single-layer EWOD chips with non-regular electrodes, which overcomes the challenges mentioned above. NR- Router is the first algorithm that can accurately route in single-layer EWOD chips with non-regular electrodes to the best of our knowledge. We construct a minimum cost flow algorithm to generate optimal routing paths followed by a light-weight model to handle flow capacity. NR-Router achieves 100% routability while minimizing wirelength at shorter run time, and generates mask files feasible for manufacturing via adjustments of design parameters. Experimental results demonstrate the robustness and efficiency of our proposed algorithm.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"88 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122965974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing 流:面向基于流的数据处理的基于读的内存计算

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712569

M. Rashed, Sven Thijssen, Sumit Kumar Jha, Fan Yao, Rickard Ewetz

{"title":"STREAM: Towards READ-based In-Memory Computing for Streaming based Data Processing","authors":"M. Rashed, Sven Thijssen, Sumit Kumar Jha, Fan Yao, Rickard Ewetz","doi":"10.1109/asp-dac52403.2022.9712569","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712569","url":null,"abstract":"Processing in-memory breaks von-Neumann based design principles to accelerate data-intensive applications. While analog in-memory computing is extremely energy-efficient, the low precision narrows the spectrum of viable applications. In contrast, digital in-memory computing has deterministic precision and can therefore be used to accelerate a broad range of high assurance applications. Unfortunately, the state-of-the-art digital in-memory computing paradigms rely on repeatedly switching the non-volatile memory devices using expensive WRITE operations. In this paper, we propose a framework called STREAM that performs READ-based in-memory computing for streaming-based data processing. The framework consists of a synthesis tool that decomposes high-level programs into in-memory compute kernels that are executed using non-volatile memory. The paper presents hardware/software co-design techniques to minimize the data movement between different nanoscale crossbars within the platform. The framework is evaluated using circuits from ISCAS85 benchmark suite and Suite-Sparse applications to scientific computing. Compared with WRITE-based in-memory computing, the READ-based in-memory computing improves latency and power consumption up to 139X and 14X, respectively.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122979040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 5

DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification DistriHD:用于图像分类的高效内存分布式二进制超维计算架构

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712589

Dehua Liang, Jun Shiomi, Noriyuki Miura, H. Awano

{"title":"DistriHD: A Memory Efficient Distributed Binary Hyperdimensional Computing Architecture for Image Classification","authors":"Dehua Liang, Jun Shiomi, Noriyuki Miura, H. Awano","doi":"10.1109/ASP-DAC52403.2022.9712589","DOIUrl":"https://doi.org/10.1109/ASP-DAC52403.2022.9712589","url":null,"abstract":"Hyper-Dimensional (HD) computing is a brain-inspired learning approach for efficient and fast learning on today's embedded devices. HD computing first encodes all data points to high-dimensional vectors called hypervectors and then efficiently performs the classification task using a well-defined set of operations. Although HD computing achieved reasonable performances in several practical tasks, it comes with huge memory requirements since the data point should be stored in a very long vector having thousands of bits. To alleviate this problem, we propose a novel HD computing architecture, called DistriHD which enables HD computing to be trained and tested using binary hypervectors and achieves high accuracy in single-pass training mode with significantly low hardware resources. DistriHD encodes data points to distributed binary hypervectors and eliminates the expensive item memory in the encoder, which significantly reduces the required hardware cost for inference. Our evaluation also shows that our model can achieve a $27.6times$ reduction in memory cost without hurting the classification accuracy. The hardware implementation also demonstrates that DistriHD achieves over $9.9times$ and $28.8times$ reduction in area and power, respectively.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123306219","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 6

Time-Triggered Scheduling for Time-Sensitive Networking with Preemption 时间敏感型抢占组网的时间触发调度

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712545

Yuanbin Zhou, Soheil Samii, P. Eles, Zebo Peng

引用次数: 6

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis 布尔重写反击:重新收敛驱动的窗口遇到重新合成

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712526

Heinz Riener, Siang-Yun Lee, A. Mishchenko, G. De Micheli

引用次数: 8

Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS 基于HLS的自动行为输入语言转换提高硬件加速器的质量

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712582

M. I. Rashid, Benjamin Carrión Schäfer

{"title":"Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS","authors":"M. I. Rashid, Benjamin Carrión Schäfer","doi":"10.1109/asp-dac52403.2022.9712582","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712582","url":null,"abstract":"High-Level Synthesis (HLS) is now part of most standard VLSI design flows and there are numerous commercial HLS tools available. One persistent problem of HLS is that the quality of results (QoR) still heavily depends on minor things like how the code is written. One additional observation that we have made in this work is that the input language used for the same HLS tool affects the QoR. HLS tools (commercial and academic) are built in a modular way which typically include a separate front-end (parser) for each input language supported. These front-ends parse the untimed behavioral descriptions, perform numerous technology independent optimizations and output a common intermediate representations (IR) for all different input languages supported. These optimizations also heavily depend on the synthesis directives set by the designer. These directives in the form of pragmas allow to control how to synthesize arrays (register or RAM), loops (unroll or not or pipeline) and functions (inline or not). We have observed that two functional equivalent behavioral descriptions with the same set of synthesis directives often lead to circuits with different QoR for the same HLS tool. Thus, automated approaches are needed to help designers to generate the best possible circuit independently of the input language used. To address this, in this work we propose using Graph Convolutional Networks (GCN) to determine the best language for a given new behavioral description and present an automated language converter for HLS.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125106920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

High-Correlation 3D Routability Estimation for Congestion-guided Global Routing 拥塞导向全局路由的高相关三维可达性估计

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/asp-dac52403.2022.9712517

Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang

{"title":"High-Correlation 3D Routability Estimation for Congestion-guided Global Routing","authors":"Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang","doi":"10.1109/asp-dac52403.2022.9712517","DOIUrl":"https://doi.org/10.1109/asp-dac52403.2022.9712517","url":null,"abstract":"Routability estimation identifies potentially congested areas in advance to achieve high-quality routing solutions. To improve the routing quality, this paper presents a deep learning-based congestion estimation algorithm that applies the estimation to a global router. Unlike existing methods based on traditional compressed 2D features for model training and prediction, our algorithm extracts appropriate 3D features from the placed netlists. Furthermore, an improved RUDY (Rectangular Uniform wire DensitY) method is developed to estimate 3D routing demands. Besides, we develop a congestion estimator by employing a U-net model to generate a congestion heatmap, which is predicted before global routing and serves to guide the initial pattern routing of a global router to reduce unexpected overflows. Experimental results show that the Pearson Correlation Coefficient (PCC) between actual and our predicted congestion is high at about 0.848 on average, significantly higher than the counterpart by 21.14%. The results also show that our guided routing can reduce the respective routing overflows, wirelength, and via count by averagely 6.05%, 0.02%, and 1.18%, with only 24% runtime overheads, compared with the state-of-the-art CUGR global router that can balance routing quality and efficiency very well. In particular, our work provides a new generic machine learning model for not only routing congestion estimation demonstrated in this paper, but also general layout optimization problems.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"257 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117354161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 4

A Voltage Template Attack on the Modular Polynomial Subtraction in Kyber Kyber中模多项式减法的电压模板攻击

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712513

Jianan Mu, Yixuan Zhao, Zongyue Wang, Jing Ye, Junfeng Fan, Shuai Chen, Huawei Li, Xiaowei Li, Yuan Cao

引用次数: 2

A Graph Neural Network Method for Fast ECO Leakage Power Optimization 基于图神经网络的ECO泄漏功率快速优化

2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC) Pub Date : 2022-01-17 DOI: 10.1109/ASP-DAC52403.2022.9712486

Kai Wang, Peng Cao

{"title":"A Graph Neural Network Method for Fast ECO Leakage Power Optimization","authors":"Kai Wang, Peng Cao","doi":"10.1109/ASP-DAC52403.2022.9712486","DOIUrl":"https://doi.org/10.1109/ASP-DAC52403.2022.9712486","url":null,"abstract":"In modern design, engineering change order (ECO) is often utilized to perform power optimization including gate-sizing and Vth-assignments, which is efficient but highly timing consuming. Many graph neural network (GNN) based methods are recently proposed for fast and accurate ECO power optimization by considering neighbors' information. Nonetheless, these works fail to learn high-quality node representations on directed graph since they treat all neighbors uniformly when gathering their information and lack local topology information from neighbors one or two-hop away. In this paper, we introduce a directed GNN based method which learns information from different neighbors respectively and contains rich local topology information, which was validated by the Opencores and IWLS 2005 benchmarks with TSMC 28nm technology. Experimental results show that our approach outperforms prior GNN based methods with at least 7.8% and 7.6% prediction accuracy improvement for seen and unseen designs respectively as well as 8.3% to 29.0% leakage optimization improvement. Compared with commercial EDA tool PrimeTime, the proposed framework achieves similar power optimization results with up to 12X runtime improvement.","PeriodicalId":239260,"journal":{"name":"2022 27th Asia and South Pacific Design Automation Conference (ASP-DAC)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125946235","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3