Improving the Quality of Hardware Accelerators through automatic Behavioral Input Language Conversion in HLS

Abstract

High-Level Synthesis (HLS) is now part of most standard VLSI design flows and there are numerous commercial HLS tools available. One persistent problem of HLS is that the quality of results (QoR) still heavily depends on minor things like how the code is written. One additional observation that we have made in this work is that the input language used for the same HLS tool affects the QoR. HLS tools (commercial and academic) are built in a modular way which typically include a separate front-end (parser) for each input language supported. These front-ends parse the untimed behavioral descriptions, perform numerous technology independent optimizations and output a common intermediate representations (IR) for all different input languages supported. These optimizations also heavily depend on the synthesis directives set by the designer. These directives in the form of pragmas allow to control how to synthesize arrays (register or RAM), loops (unroll or not or pipeline) and functions (inline or not). We have observed that two functional equivalent behavioral descriptions with the same set of synthesis directives often lead to circuits with different QoR for the same HLS tool. Thus, automated approaches are needed to help designers to generate the best possible circuit independently of the input language used. To address this, in this work we propose using Graph Convolutional Networks (GCN) to determine the best language for a given new behavioral description and present an automated language converter for HLS.