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2006 IEEE International Behavioral Modeling and Simulation Workshop最新文献

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Verification of CML circuits used in PLL contexts with Verilog-AMS 用Verilog-AMS验证锁相环环境中使用的CML电路
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283477
J. David
{"title":"Verification of CML circuits used in PLL contexts with Verilog-AMS","authors":"J. David","doi":"10.1109/BMAS.2006.283477","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283477","url":null,"abstract":"CML (current-mode logic) circuits are used in very high-speed applications where standard CMOS gates not perform. Applications of CML logic are introduced, focusing on the clock divider for PLL's operating above 1-2GHz common in communication circuits. An overview of CML circuits and their operation is provided. Starting with a Verilog-A model of a basic gate, the development of connects elements and rules are explained, and applied to the resulting mixed signal model of the gate. Finally the application of this circuit to the PLL and the resulting simulation performance improvements presented","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124638251","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Improving the performance of an FPGA based Model design for sensor monitoring using PlanAhead tool 利用PlanAhead工具改进基于FPGA的传感器监测模型设计
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283476
K. Arshak, E. Jafer, C. Ibala
{"title":"Improving the performance of an FPGA based Model design for sensor monitoring using PlanAhead tool","authors":"K. Arshak, E. Jafer, C. Ibala","doi":"10.1109/BMAS.2006.283476","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283476","url":null,"abstract":"The study in this paper is focused on the improvement of a field programmable gate arrays (FPGA) based design using a hierarchical analysis tool offered by XILINX PlanAheadtrade. During this work, PlanAhead software is used to address any problems on the physical side of our FPGA design flow in order to add more visibility and control. The target system is reading analog information recorded by a biomedical sensor in a transmitting unit attached to the patient. The recorded data is converted digitally using analog to digital converter (ADC) and sent to FSK transmitter through FPGA. Verilog HDL has been used to develop and implement the required functions of the FPGA, such as bus interfacing, data buffering, compression and framing. The system performance has been optimized using a recent comprehensive tool in order to reach and maintain the goals of the design","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124368275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Functional Verification of Radio Frequency SoCs using Mixed-Mode and Mixed-Domain Simulations 基于混合模式和混合域仿真的射频soc功能验证
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283485
S. Joeres, Stefan Heinen
{"title":"Functional Verification of Radio Frequency SoCs using Mixed-Mode and Mixed-Domain Simulations","authors":"S. Joeres, Stefan Heinen","doi":"10.1109/BMAS.2006.283485","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283485","url":null,"abstract":"The main focus of this work is the functional verification of radio frequency (RF) transceivers and RF systems on chip (SoCs). The use of enhanced baseband behavioral description models for an industrial available multiband, low IF GSM receiver is demonstrated. The necessity of functional verification when dealing with complex baseband signals and mixing operations with high/low sideband possibilities is shown. Future demands on language constructs and their implementations into the design flow are presented. Fundamental simulation comparisons for different implementation levels and proposals for new constructs to ensure functionality and connectivity between advanced behavioral description level and transistor schematics are made. This paper concludes with a suggestion for an extension of the Verilog-HDL-family to aid SoC designers in their effort to shorten the time to market and demonstrates the possible benefits of upcoming systemVerilog constructs","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127794579","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 16
A New Approach for Modeling the Nonlinearity of Analog to Digital Converters Based on Spectral Components 基于频谱分量的模数转换器非线性建模新方法
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283481
N. Saada, R. Guindi, A. Salama
{"title":"A New Approach for Modeling the Nonlinearity of Analog to Digital Converters Based on Spectral Components","authors":"N. Saada, R. Guindi, A. Salama","doi":"10.1109/BMAS.2006.283481","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283481","url":null,"abstract":"This paper presents a novel modeling approach for analog to digital converters (ADCs). The non linearity of the converter is modeled using a linear combination of Chebyshev polynomials. The model relies on a fast Fourier transform (FFT) test applied to the output of the ADC. The harmonics extracted from the FFT test are the coefficients of the Chebyshev polynomials. The model appears to be much faster, compared to real circuits and models developed with other techniques, without losing much accuracy. The proposed model is convenient for all architectures of ADCs with high resolution bits","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128173867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Event-Driven Modeling and Simulation of an Digital PLL 数字锁相环的事件驱动建模与仿真
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283472
J. Zhuang, Q. Du, T. Kwasniewski
{"title":"Event-Driven Modeling and Simulation of an Digital PLL","authors":"J. Zhuang, Q. Du, T. Kwasniewski","doi":"10.1109/BMAS.2006.283472","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283472","url":null,"abstract":"An event-driven modeling and simulation technique, implemented in Matlab is presented in this paper. It enables rapid and accurate simulation as it only calculates the time instants of interest. This technique is successfully applied to behavioral modeling and simulation of a digital phase-locked loop. The simulation environment retains the flexibility of modeling and mathematical manipulation that characterizes Matlab. For example, it allows time-domain modeling phase noise of each component of a digital PLL","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114508020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 19
Average Behavioral Modeling Technique for Switched-Capacitor Voltage Converters 开关电容电压变换器的平均行为建模技术
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283479
M. Fikry, M. Dessouky, H. Ghitani
{"title":"Average Behavioral Modeling Technique for Switched-Capacitor Voltage Converters","authors":"M. Fikry, M. Dessouky, H. Ghitani","doi":"10.1109/BMAS.2006.283479","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283479","url":null,"abstract":"This paper applies an average modeling technique to different types of switched-capacitor DC-DC converters, taking into account the circuit non-ideal parameters. An extensive set of experiments were carried out to test the validity of each model. The results show acceptable accuracy and simulation speed gain of several thousand times. This speed gain is achieved due to relaxation of the simulation timestep as opposed to traditional modeling and simulation techniques, where the simulator timestep is bound by the switching frequency. This modeling approach is most suitable for system level simulations where accuracy can be traded-off for speed","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128416827","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
A Referenced Geometry Based Configuration Scalable Mextram Model for Bipolar Transistors 一种基于参考几何的双极晶体管配置可扩展极值模型
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283469
H. Wu, S. Mijalkovic, J. Burghartz
{"title":"A Referenced Geometry Based Configuration Scalable Mextram Model for Bipolar Transistors","authors":"H. Wu, S. Mijalkovic, J. Burghartz","doi":"10.1109/BMAS.2006.283469","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283469","url":null,"abstract":"A behavioral reference based model for configuration scaling of bipolar transistor model parameters is proposed. The model is applicable to bipolar technologies with one or two collector contacts and different number of emitters. The effectiveness of the proposed scaling methodology is verified in case studies using advanced high-speed SiGe HBT technology","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127136310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Statistical Gate Level Simulation via Voltage Controlled Current Source Models 通过电压控制电流源模型的统计门电平仿真
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283464
Bao Liu, A. Kahng
{"title":"Statistical Gate Level Simulation via Voltage Controlled Current Source Models","authors":"Bao Liu, A. Kahng","doi":"10.1109/BMAS.2006.283464","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283464","url":null,"abstract":"Current source based gate models achieve orders of magnitude of improved accuracy than the previous voltage source and effective load capacitance based gate models. Increasingly significant variability in DSM and nanometer scale VLSI designs calls for statistical analysis and optimization. In this paper, we propose a more efficient statistical gate level simulation method than Monte Carlo simulation based on current source based gate models. We represent a variational voltage waveform of any shape by a time domain statistical variable, and compute variational gate output voltage waveform by time domain integration of statistical variables which takes into account input voltage waveform variation and process variations with their correlations. Our experiments show that our statistical gate level simulation achieves over 20times efficiency improvement with an average of 4.1%(22.3%) accuracy loss for the means (standard deviations) of gate delay compared with 1000times Monte Carlo simulation based on current source based gate models","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132839168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Automated Receiver Design and Optimization for 4G Wireless Communication Systems 4G无线通信系统自动接收机设计与优化
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283483
D.R. de Llera Gonzalez, A. Rusu, M. Ismail
{"title":"Automated Receiver Design and Optimization for 4G Wireless Communication Systems","authors":"D.R. de Llera Gonzalez, A. Rusu, M. Ismail","doi":"10.1109/BMAS.2006.283483","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283483","url":null,"abstract":"This paper presents the design methodology and underlying algorithms of a tool developed for automated receiver design and optimization for fourth generation (4G) wireless communication systems. An algorithm to systematically design and optimize the receiver budget for the multi-standard case is introduced. The goal of this algorithm is to find a multi-standard receiver budget that meets or exceeds the specs of the addressed wireless standards while keeping the requirements of each of the receiver blocks as relaxed as possible. This tool offers RF engineers a deep insight into the receiver behavior at a very early stage of the design flow. It models the impact of some circuit non-idealities using a high level of abstraction. This reduces the number of design iterations and, thus, the time-to-market of the solution. The reuse of already available intellectual property (IP) blocks is also considered in the tool. This can result in a significant cost, reduction of the receiver implementation","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133246742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Nanometer Wireless Transceiver Modeling using Verilog-AMS and SystemC 基于Verilog-AMS和SystemC的纳米无线收发器建模
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283486
M. Hujer, R. Maňásek, J. O'Mahony, P. Feerick, M. Barry, B. Walsh
{"title":"Nanometer Wireless Transceiver Modeling using Verilog-AMS and SystemC","authors":"M. Hujer, R. Maňásek, J. O'Mahony, P. Feerick, M. Barry, B. Walsh","doi":"10.1109/BMAS.2006.283486","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283486","url":null,"abstract":"This paper presents an original methodology for use of Verilog-AMS and SystemC to model a highly integrated wireless transceiver. Novel structures allow the model to be reconfigurable for extensive early architectural analysis and easy re-mapping to new wireless standards and applications. Matlab plots are used to demonstrate the usefulness of the model simulations in the analysis of complex combined digital and analog functionality such as automatic gain control and DC offset correction. Performance results for the simulations as well as development effort are also presented thus showing how this methodology is well suited to the modeling of integrated nanometer wireless transceivers","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114558078","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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