Verification of CML circuits used in PLL contexts with Verilog-AMS

Abstract

CML (current-mode logic) circuits are used in very high-speed applications where standard CMOS gates not perform. Applications of CML logic are introduced, focusing on the clock divider for PLL's operating above 1-2GHz common in communication circuits. An overview of CML circuits and their operation is provided. Starting with a Verilog-A model of a basic gate, the development of connects elements and rules are explained, and applied to the resulting mixed signal model of the gate. Finally the application of this circuit to the PLL and the resulting simulation performance improvements presented