Statistical Gate Level Simulation via Voltage Controlled Current Source Models

Abstract

Current source based gate models achieve orders of magnitude of improved accuracy than the previous voltage source and effective load capacitance based gate models. Increasingly significant variability in DSM and nanometer scale VLSI designs calls for statistical analysis and optimization. In this paper, we propose a more efficient statistical gate level simulation method than Monte Carlo simulation based on current source based gate models. We represent a variational voltage waveform of any shape by a time domain statistical variable, and compute variational gate output voltage waveform by time domain integration of statistical variables which takes into account input voltage waveform variation and process variations with their correlations. Our experiments show that our statistical gate level simulation achieves over 20times efficiency improvement with an average of 4.1%(22.3%) accuracy loss for the means (standard deviations) of gate delay compared with 1000times Monte Carlo simulation based on current source based gate models