{"title":"Improving the performance of an FPGA based Model design for sensor monitoring using PlanAhead tool","authors":"K. Arshak, E. Jafer, C. Ibala","doi":"10.1109/BMAS.2006.283476","DOIUrl":null,"url":null,"abstract":"The study in this paper is focused on the improvement of a field programmable gate arrays (FPGA) based design using a hierarchical analysis tool offered by XILINX PlanAheadtrade. During this work, PlanAhead software is used to address any problems on the physical side of our FPGA design flow in order to add more visibility and control. The target system is reading analog information recorded by a biomedical sensor in a transmitting unit attached to the patient. The recorded data is converted digitally using analog to digital converter (ADC) and sent to FSK transmitter through FPGA. Verilog HDL has been used to develop and implement the required functions of the FPGA, such as bus interfacing, data buffering, compression and framing. The system performance has been optimized using a recent comprehensive tool in order to reach and maintain the goals of the design","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2006 IEEE International Behavioral Modeling and Simulation Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BMAS.2006.283476","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
Abstract
The study in this paper is focused on the improvement of a field programmable gate arrays (FPGA) based design using a hierarchical analysis tool offered by XILINX PlanAheadtrade. During this work, PlanAhead software is used to address any problems on the physical side of our FPGA design flow in order to add more visibility and control. The target system is reading analog information recorded by a biomedical sensor in a transmitting unit attached to the patient. The recorded data is converted digitally using analog to digital converter (ADC) and sent to FSK transmitter through FPGA. Verilog HDL has been used to develop and implement the required functions of the FPGA, such as bus interfacing, data buffering, compression and framing. The system performance has been optimized using a recent comprehensive tool in order to reach and maintain the goals of the design