2006 IEEE International Behavioral Modeling and Simulation Workshop最新文献

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System-Level Time-Domain Behavioral Modeling for A Mobile WiMax Transceiver 移动WiMax收发器的系统级时域行为建模
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283484
Jie He, Jun Seok Yang, Yongsup Kim, A. Kim
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引用次数: 22
Simulation of Power Grid Networks Considering Wires and Lognormal Leakage Current Variations 考虑导线和对数正态泄漏电流变化的电网仿真
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283473
N. Mi, Jeffrey Fan, Sheldon X.-D. Tan
{"title":"Simulation of Power Grid Networks Considering Wires and Lognormal Leakage Current Variations","authors":"N. Mi, Jeffrey Fan, Sheldon X.-D. Tan","doi":"10.1109/BMAS.2006.283473","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283473","url":null,"abstract":"As the technology scales into 90 nm and below, process-induced variations become more pronounced. In this paper, we propose an efficient stochastic method for analyzing the voltage drop variations of on-chip power grid networks, considering both wire and log-normal leakage current variations. The new analysis is based on the Hermite polynomial chaos (PC) representation of random processes. Different from the existing Hermite PC based method for power grid analysis, which considers only wire variations and model all the random variations as Gaussian processes. The new method considers both wire variations and leakage current variations. We model the variational sub-threshold leakage currents as log-normal distribution random variables. Our experiment results show that the new method is more accurate than the Gaussian-only Hermite PC method using the Taylor expansion method for analyzing leakage current variations, and two orders of magnitude faster than the Monte Carlo method with small variance errors","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"12 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134299147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Expected Performance Centering for Analog/RF Designs 模拟/射频设计的预期性能中心
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283482
Bao Liu, A. Kahng
{"title":"Expected Performance Centering for Analog/RF Designs","authors":"Bao Liu, A. Kahng","doi":"10.1109/BMAS.2006.283482","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283482","url":null,"abstract":"We unite the conventional analog/RF design objectives such as design centering and performance targeting and propose a generalized analog/RF design objective. We propose expected performance centering, i.e., to maximize the expected performance margin of a circuit under process and environmental variations for topology selection with performance specification in a hierarchical design. We develop three methods to compute expected performance margin. Our experimental results show improved expected performance margin achieved by the proposed expected performance centering technique","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"53 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134530867","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design 基于自旋传递转矩的磁- cmos混合设计磁隧道结装置宏观模型
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283467
Weisheng Zhao, E. Belhaire, Q. Mistral, C. Chappert, V. Javerliac, Bernard Dieny, E. Nicolle
{"title":"Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design","authors":"Weisheng Zhao, E. Belhaire, Q. Mistral, C. Chappert, V. Javerliac, Bernard Dieny, E. Nicolle","doi":"10.1109/BMAS.2006.283467","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283467","url":null,"abstract":"The development of hybrid magnetic-CMOS circuits such as MRAM (magnetic RAM) and magnetic logic circuit requires efficient simulation models for the magnetic devices. A macro-model of magnetic tunnel junction (MTJ) is presented in this paper. This device is the most commonly used magnetic components in CMOS circuits. This model is based on spin-transfer torque (STT) writing approach. This very promising approach should constitute the second generation of MRAM switching technology; it features small switching current (~120uA) and high programming speed (<1ns). The macro-model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.0.32 simulator. Many experimental parameters are integrated in this model to improve the simulation accuracy. So, the model can efficiently be used to design hybrid magnetic CMOS circuits","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"12 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114114691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 121
Mixed-Signals Design Automation using the MIX-SYN Framework 使用MIX-SYN框架的混合信号设计自动化
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 2006-09-01 DOI: 10.1109/BMAS.2006.283478
E. Liao, A. Postula
{"title":"Mixed-Signals Design Automation using the MIX-SYN Framework","authors":"E. Liao, A. Postula","doi":"10.1109/BMAS.2006.283478","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283478","url":null,"abstract":"This paper demonstrates how the MIX-SYN framework can fast-track the design of analogue and mixed-signals integrated circuits, traditionally designed using time-consuming techniques. By integrating different levels of design abstraction and their simulation environments, MIX-SYN aims to bridge the existing design discontinuity of transferring algorithm to functional design. It does not perform general analogue synthesis, but uses a mix of knowledge-based and analytic-based approaches to help the designer rapidly explore the design space and arrive at a circuit solution","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124262755","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Mixed Modeling of a SAW Delay Line using VHDL 基于VHDL的声波延迟线混合建模
2006 IEEE International Behavioral Modeling and Simulation Workshop Pub Date : 1900-01-01 DOI: 10.1109/BMAS.2006.283466
W. Wilson, G. Atkinson
{"title":"Mixed Modeling of a SAW Delay Line using VHDL","authors":"W. Wilson, G. Atkinson","doi":"10.1109/BMAS.2006.283466","DOIUrl":"https://doi.org/10.1109/BMAS.2006.283466","url":null,"abstract":"To aid in the development of SAW sensors for aerospace applications we have created a model of a SAW delay line using VHDL. The model implements the impulse response method to calculate the frequency response, impedance, and insertion loss. The model includes optimization for the number of finger pairs in the IDTs and for the aperture height. This paper presents the model and the results from the model for a SAW delay line design","PeriodicalId":235383,"journal":{"name":"2006 IEEE International Behavioral Modeling and Simulation Workshop","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116022273","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
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