2014 International 3D Systems Integration Conference (3DIC)最新文献_第3页

An impact of circuit scale on the performance of 3-D stacked arithmetic units 电路规模对三维堆叠算术单元性能的影响

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152185

J. Tada, Ryusuke Egawa, Hiroaki Kobayashi

{"title":"An impact of circuit scale on the performance of 3-D stacked arithmetic units","authors":"J. Tada, Ryusuke Egawa, Hiroaki Kobayashi","doi":"10.1109/3DIC.2014.7152185","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152185","url":null,"abstract":"Recently, the 3-D stacked integrated circuit technology has been expected to overcome the limitations in the design of the 2-D implemented microprocessors. This paper examines the potential of 3-D integration in design and implementation of large-scale arithmetic units. In this paper, 3-D stacked parallel multipliers with various operand sizes are designed, and the effect of circuit scale on the performance of 3-D stacked multipliers is discussed. In the design of a large-scale parallel multiplier, a lot of through-silicon-vias are required by the conventional partitioning pattern. This paper proposes a partitioning pattern suitable for a large-scale 3-D stacked parallel multiplier. The proposed partitioning pattern aims to reduce the number of TSVs with a large-scale parallel multiplier. Based on the proposed partitioning pattern, 3-D stacked 32, 64, and 128-bit multipliers are designed and evaluated. The proposed partitioning pattern achieves a 13.4% reduction in critical path delay and a 10.4% reduction in power consumption compared to the 2-D implementation, in the case of an 128-bit four-layer implemented 3-D stacked multiplier.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117033011","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 3

Electrical model and characterization of Through Silicon Capacitors (TSC) in silicon interposer 硅中间层中通硅电容器(TSC)的电学模型与特性

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152152

K. Dieng, P. Artillan, C. Bermond, O. Guiller, T. Lacrevaz, S. Joblot, G. Houzet, A. Farcy, Y. Lamy, B. Fléchet

引用次数: 6

A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests 成本效益分析:缺陷聚类对粘结前测试必要性的影响

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152176

Qiaosha Zou, Matthew Poremba, Yuan Xie

{"title":"A cost benefit analysis: The impact of defect clustering on the necessity of pre-bond tests","authors":"Qiaosha Zou, Matthew Poremba, Yuan Xie","doi":"10.1109/3DIC.2014.7152176","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152176","url":null,"abstract":"The emerging three-dimensional integrated circuit (3D IC) provides a promising solution for sustainable computer performance scaling. However, the high cost due to the complex pre-bond/intermediate testing and the low compound yield hinder the commercial adoption of 3D ICs. The defect clustering is found biasing the yield prediction, resulting in an unrealistic cost estimation at the early design stage. Under defect clusterings, it is possible that we eliminate the pre-bond/intermediate test. Moreover, components in a chip might be functional even with defects, which leads to the partially functional dies. Therefore, in this work, we propose a framework to analyze the cost benefit with test elimination and partially functional dies. To support our proposed framework, a hierarchical yield model and an analytical model for test elimination considering defect clustering are provided. Through analyzing the impact of the pre-bond/intermediate test elimination on the final stacking cost with our framework, we show that the wafer cost is the most important factor on the test elimination. Moreover, further cost saving can be obtained by combining partially functional dies with test elimination.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130385373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Innovative SiC over Si photodiode based dual-band, 3D integrated detector 创新的SiC over Si光电二极管为基础的双带，3D集成探测器

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152181

A. Kociubiński, M. Duk, T. Bieniek, G. Janczyk, M. Borecki

引用次数: 3

Fault localisation of defects using Electro Optical Terahertz Pulse Reflectometry and 3D EM modelling with Virtual Known Good Device 利用电光太赫兹脉冲反射仪和虚拟已知好器件的三维电磁建模进行缺陷故障定位

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152159

E. Kowalczuk, A. Bhattacharya, Ka Chung Lee, J. Alton, M. Igarashi, S. Barbeau

引用次数: 4

Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation 异构3D集成电路的热挑战和气隙热隔离的机遇

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152174

Yang Zhang, Thomas E. Sarvey, M. Bakir

引用次数: 11

Design rule check and layout versus schematic for 3D integration and advanced packaging 3D集成和先进封装的设计规则检查和布局与原理图

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152150

R. Fischbach, A. Heinig, P. Schneider

引用次数: 2

Bumpless interconnects formed with nanowire ACF for 3D applications 用纳米线ACF形成的无凹凸互连用于3D应用

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152154

J. Tao, A. Mathewson, K. Razeeb

引用次数: 1

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation 集群的三维网格:用于3D-FPGA实现的另一种统一的高性能互连架构

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152149

S. Chtourou, M. Abid, V. Pangracious, Emna Amouri, Z. Marrakchi, H. Mehrez

{"title":"Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation","authors":"S. Chtourou, M. Abid, V. Pangracious, Emna Amouri, Z. Marrakchi, H. Mehrez","doi":"10.1109/3DIC.2014.7152149","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152149","url":null,"abstract":"In this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131546483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Advanced 3D mixed-signal processor for infrared focal plane arrays: Fabrication and test 用于红外焦平面阵列的先进3D混合信号处理器:制造和测试

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152142

D. Temple, D. Malta, E. Vick, M. Lueck, S. Goodwin, M. Muzilla, C. Masterjohn, M. Skokan

引用次数: 6