2014 International 3D Systems Integration Conference (3DIC)最新文献

Small-diameter TSV reveal process using direct Si/Cu grinding and metal contamination removal

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152144

N. Watanabe, M. Aoyagi, Daisuke Katagawa, T. Bandoh, Takahiko Mitsui, E. Yamamoto

引用次数: 5

Analysis of thermal stress distribution for TSV with novel structure 新型结构TSV的热应力分布分析

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152168

W. Feng, N. Watanabe, H. Shimamoto, K. Kikuchi, M. Aoyagi

{"title":"Analysis of thermal stress distribution for TSV with novel structure","authors":"W. Feng, N. Watanabe, H. Shimamoto, K. Kikuchi, M. Aoyagi","doi":"10.1109/3DIC.2014.7152168","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152168","url":null,"abstract":"Through Silicon Via (TSV) plays a key role in accomplishing 3D IC integration. In most common approaches, TSV is filled with copper. Due to large mismatch in Coefficients of Thermal Expansion (CTE) between the copper via and the silicon of TSV, significant thermal stresses will be induced at the interfaces of Cu/dielectric layer (usually SiO2) and dielectric layer/Si, which would lead to various reliability and electrical performance issues. As a solution, a novel structure TSV (Annular-Trench-Isolated TSV: ATI TSV) was proposed to optimize the thermal stress distribution. A ring of Si is remained between Cu and SiO2 during print process. The better thermal properties of ATI TSV was revealed by Finite Element Method simulation. The thermal stress level of ATI TSV is compared to most common cylindrical TSV (regular TSV) and annular TSV. Due to the large CTE mismatch between copper and silicon, the stress is concentrated at the interface of Cu/Si inside TSV under thermal load. In case of 5 μm TSV diameter, thermal stress with level of less than 30 MPa is achieved in silicon substrate of ATI TSV with 80% reduction comparing to regular TSV. The silicon ring thickness is constant as 1 μm in this study. With downsizing TSV diameter, the volume ratio of silicon ring to copper core increases. Therefore, the effect of stress concentration at the interface of Cu/Si inside TSV enhanced with TSV scaling down. Further reducation of stress in silicon substrate can be achieved by thicken silicon ring in ATI TSV.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116041310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 11

On-chip checkpointing with 3D-stacked memories 带有3d堆叠存储器的片上检查点

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152173

Masayuki Sato, Ryusuke Egawa, H. Takizawa, Hiroaki Kobayashi

引用次数: 2

Thermal performance of 3D ICs: Analysis and alternatives 三维集成电路的热性能:分析和替代方案

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152163

C. Santos, P. Vivet, J. Colonna, P. Coudrain, R. Reis

{"title":"Thermal performance of 3D ICs: Analysis and alternatives","authors":"C. Santos, P. Vivet, J. Colonna, P. Coudrain, R. Reis","doi":"10.1109/3DIC.2014.7152163","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152163","url":null,"abstract":"3D ICs are assumed to suffer from stronger thermal issues when compared to equivalent implementations in traditional single-die integration technologies. Based on this assumption, heat dissipation is frequently pointed as one of the remaining challenges in the promising 3D integration technology. This work brings an overview of the thermal impact of the 3D integration technology, providing means to investigate causes and alternative solution for the existing thermal issues in 3D ICs. A complete chip-package-board system is used to evaluate the thermal performance of a memory-on-logic 3D circuit. Thermal simulations and silicon measurements from two fabricated versions of a SoC instrumented with integrated heaters and thermal sensors are compared to reveal the temperature profile changes resulting from 3D integration. This work also provides a comprehensive discussion of the four main aspects differentiating heat dissipation in 3D ICs: chip footprint, die thickness, inter-die interface and TSVs. This study demonstrates, for instance, that non-thinned stacked dies may act as heat spreaders and help to alleviate hotspot issues while TSVs are in fact not effective for thermal mitigation. Lastly, this work proposes the use of graphite-based heat spreaders as an alternative to compensate the poor heat dissipation properties exhibited in 3D ICs. Simulation results show a temperature reduction of up to 45μC and suggest this is a potential cost-effective method for thermal management. The discussion presented in this work aims to understand the thermal impact of technology parameters inherent in 3D integration and supports system architects and designers to take early design decisions and prevent thermal issues.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117020970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 20

Cooling from the bottom side (laminate (substrate) side) of a three-dimensional (3D) chip stack 从三维(3D)芯片堆栈的底部侧(层压板(基板)侧)进行冷却

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152164

Keiji Matsumoto, H. Mori, Y. Orii

引用次数: 2

Leveraging 3D-IC for on-chip timing uncertainty measurements 利用3D-IC进行片上时序不确定度测量

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152172

Randy Widialaksono, Wenxu Zhao, W. R. Davis, P. Franzon

引用次数: 2

Thermal implications of mobile 3D-ICs 移动3d - ic的热影响

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152160

Mehdi Saedi, K. Samadi, Arpit Mittal, R. Mittal

引用次数: 9

Micro-XRD investigation of fine-pitch Cu-TSV induced thermo-mechanical stress in high-density 3D-LSI 高密度3D-LSI中Cu-TSV诱发热机械应力的微观xrd研究

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152158

M. Murugesan, T. Fukushima, J. Bea, K. Lee, M. Koyanagi, Y. Imai, S. Kimura, Tetsu Tanaka

引用次数: 2

Analysis of 3D interconnect performance: Effect of the Si substrate resistivity 三维互连性能分析:Si衬底电阻率的影响

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152156

X. Sun, G. V. D. Plas, M. Detalle, E. Beyne

引用次数: 5

Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding Cu-SiO2直接杂化键合可靠高密度Cu-Cu互连研究进展

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7274306

Y. Beilliard, S. Moreau, L. Cioccio, P. Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P. Jouneau, E. Rolland, T. Signamarcheix

{"title":"Advances toward reliable high density Cu-Cu interconnects by Cu-SiO2 direct hybrid bonding","authors":"Y. Beilliard, S. Moreau, L. Cioccio, P. Coudrain, G. Romano, A. Nowodzinski, F. Aussenac, P. Jouneau, E. Rolland, T. Signamarcheix","doi":"10.1109/3DIC.2014.7274306","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7274306","url":null,"abstract":"Cu-SiO2 direct hybrid bonding is considered as one of the most promising approaches for matching the needs of three dimensional integrated circuits (3D-IC). In this paper we present the results of a complete morphological, electrical and reliability study conducted on four-layer copper structures realized by Cu-SiO2 direct hybrid bonding. Ultra-fine 7 μm pitch, 3 μm × 3 μm pads daisy chains with up to 30 160 connections are bonded with submicron accuracy, matching the interconnection needs in upcoming 3D circuits. A focus is paid on the influence of the temperature of annealing on the bonding quality and electrical performances. Thanks to SEM, FIB/SEM tomography, AFM, TEM and TEM-EDX analysis, the morphology of the bonded structures is described. Electrical parametric tests exhibit very low resistance structures, with high functional yields and low variability. State-of-the-art contact resistivity is obtained for 200 and 400 °C treatments. Unbiased HAST, temperature cycling and temperature storage tests demonstrate excellent reliability performances. Finally, an electromigration resistance comparative study is conducted on bonded copper lines with TaN/Ta and TiN diffusion barriers.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113984163","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 32