2014 International 3D Systems Integration Conference (3DIC)最新文献_第2页

Designing vertical bandwidth reconfigurable 3D NoCs for many core systems 为多个核心系统设计垂直带宽可重构3D noc

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152186

Qiaosha Zou, J. Zhan, Fen Ge, Matthew Poremba, Yuan Xie

{"title":"Designing vertical bandwidth reconfigurable 3D NoCs for many core systems","authors":"Qiaosha Zou, J. Zhan, Fen Ge, Matthew Poremba, Yuan Xie","doi":"10.1109/3DIC.2014.7152186","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152186","url":null,"abstract":"As the number of processing elements increases in a single chip, the interconnect backbone becomes more and more stressed when serving frequent memory and cache accesses. Network-on-Chip (NoC) has emerged as a potential solution to provide a flexible and scalable interconnect in a planar platform. In the mean time, three-dimensional (3D) integration technology pushes circuit design beyond Moore's law and provides short vertical connections between different layers. As a result, the innovative solution that combines 3D integrations and NoC designs can further enhance the system performance. However, due to the unpredictable workload characteristics, NoC may suffer from intermittent congestions and channel overflows, especially when the network bandwidth is limited by the area and energy budget. In this work, we explore the performance bottlenecks in 3D NoC, and then leverage redundant TSVs, which are conventionally used for fault tolerance only, as vertical links to provide additional channel bandwidth for instant throughput improvement. Moreover, these shared redundant links can be dynamically allocated to the stressed routers for congestion alleviation. Experimental results show that our proposed NoC design can provide up to 40% performance improvement, with less than 1.5% area overhead.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116781589","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Substrate monitoring system for inspecting defects in TSV-based data buses 基于tsv的数据总线缺陷检测基板监测系统

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152179

Y. Araga, K. Kikuchi, M. Aoyagi

{"title":"Substrate monitoring system for inspecting defects in TSV-based data buses","authors":"Y. Araga, K. Kikuchi, M. Aoyagi","doi":"10.1109/3DIC.2014.7152179","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152179","url":null,"abstract":"Three dimensional ICs are expected to bring about a new generation of integration by allowing for a smaller footprint, faster operation, and lower energy consumption. Manufacturing defects in through-silicon via (TSV) and disconnection defects among tiers are concerns in this new technology. To prevent yield loss from these defects, confirming known-good-die (KGD) and known-good-stacks (KGS) by test is a critical issue. In this paper, embedded test circuitry is proposed to guarantee KGD and KGS by measuring noise on the silicon substrate. The proposed test circuit consists of simple circuitry and potentially can test multiple TSVs with just a single channel of test circuitry. Testing by using substrate noise measurements does not require direct electrical connections. Hence, the proposed test structure does not invade the original circuit design. An analytical model is created to indicate effectivity of the test structure. Analytical result shows a single channel of test circuitry can test 72 TSVs of the same pitch, such as would be encountered in Wide-I/O. Use of the test structure both during initial calibration and then during actual product use are discussed.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124271005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Metal coated polymer spheres for compliant fine pitch ball grid arrays 柔性细间距球栅阵列用金属包覆聚合物球

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152177

D. N. Wright, M. Taklo, Astrid-Sofie B. Vardøy, H. Kristiansen

{"title":"Metal coated polymer spheres for compliant fine pitch ball grid arrays","authors":"D. N. Wright, M. Taklo, Astrid-Sofie B. Vardøy, H. Kristiansen","doi":"10.1109/3DIC.2014.7152177","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152177","url":null,"abstract":"The further development of heterogeneous 3D integration involving electrical connections between layers of various materials demand compliant fine pitch interconnects to allow for the varying expansion as a function of temperature of the different materials involved. However, most available fine pitch interconnects, like micro bumps and copper pillars, are not particularly compliant whereas available compliant interconnects, like plastic core solder balls, are not fine pitch. In this work we present a novel process for achieving a fine pitch ball grid array comprised of compliant interconnects using singular 30 μm metal coated polymer spheres (MPS) in conjunction with nano-particle silver conductive ink. Results show that when an MPS attached to a chip is flip chip assembled onto a substrate with a 1.3 μm thick layer of wet conductive ink, the ink is drawn up along the MPS surface to such an extent that it a forms a bonding neck between the MPS and the chip surface. It also created a coating up to 1.5 μm on the MPS. Shear testing of the assembly gave values of up to 0.67 grams per MPS. This strength can be increased further by optimizing the process and to utilize such an interconnect in combination with underfill can result in sufficient reliability for several applications. The volume of ink required to form such bonds is in the same range as industrial ink jet nozzles can deliver. MPS was applied onto a substrate which had been jetted with a regular pattern of ink droplets. It was found that the MPS were observed to have had a certain extent of self-alignment along the jetted pattern.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 2

Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects 用于3D互连的Au-NiW机械柔性互连(mfi)和TSV集成

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152166

Chaoqi Zhang, Paragkumar Thadesar, Muneeb Zia, Thomas E. Sarvey, M. Bakir

引用次数: 4

Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICs 2.5D和3D集成电路中由tsv和rdd组成的磁耦合电流探测结构

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152151

Jonghoon J. Kim, Bumhee Bae, Sukjin Kim, Sunkyu Kong, Heegon Kim, D. Jung, Joungho Kim

{"title":"Magnetically-coupled current probing structure consisting of TSVs and RDLs in 2.5D and 3D ICs","authors":"Jonghoon J. Kim, Bumhee Bae, Sukjin Kim, Sunkyu Kong, Heegon Kim, D. Jung, Joungho Kim","doi":"10.1109/3DIC.2014.7152151","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152151","url":null,"abstract":"Simultaneous switching current (SSC) drawn by integrated circuits (ICs) creates simultaneous switching noise (SSN) on power nets, which causes a number of SI/PI problems, such as reduced noise margin and eye opening with increased SSN. Analyzing the effects of SSC and SSN is especially important for ICs targeted for mobile applications whose operating frequency keeps on increasing with decreasing operating voltage. Therefore, it is of utmost importance to measure SSCs for a thorough analysis of high-speed systems. In this paper, a magnetically-coupled current probing structure consisting of TSVs and RDLs, namely TSV-based Current Probe (TCP), is proposed for measuring the SSC resulting from the logical activity of the I/O buffers in 2.5D and 3D-ICs. SSCs are found by capturing the magnetic flux induced by the SSC of interest with the proposed current probing structure, and then reconstructing the original current waveform using the transfer impedance profile. Through a series of simulation in frequency and time domains, we verified the performance of the proposed probing structure consisting of TSVs and RDLs and proved it can effectively measure the SSC. Lastly, a test vehicle is fabricated on package level for experimental verification of the proposed probing structure.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"9 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120897018","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 1

Novel methodology for 3D MEMS-IC design and co-simulation on MEMS microphone smart system example 一种新颖的MEMS- ic三维设计方法及MEMS麦克风智能系统联合仿真实例

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152184

T. Bieniek, G. Janczyk, M. Ekwinska, T. Budzynski, P. Gluszko, P. Grabiec, A. Kociubiński

引用次数: 2

Effects of electro-less Ni layer as barrier/seed layers for high reliable and low cost Cu TSV 无电解镍层作为高可靠性、低成本铜 TSV 的阻挡层/种子层的效果

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152153

K. Lee, C. Nagai, A. Nakamura, J. Bea, M. Murugesan, T. Fukushima, Tanaka Tanaka, M. Koyanagi

引用次数: 7

Analysis and optimization of a power distribution network in 2.5D IC with glass interposer 带玻璃中间层的2.5D集成电路配电网的分析与优化

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152180

Youngwoo Kim, Jonghyun Cho, Kiyeong Kim, Heegon Kim, Joungho Kim, S. Sitaraman, V. Sundaram, R. Tummala

引用次数: 6

Cu seeding using electroless deposition on Ru liner for high aspect ratio through-Si vias 用化学沉积法在Ru衬垫上播种Cu以获得高纵横比的si通孔

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152147

F. Inoue, H. Philipsen, M. V. Veen, K. Vandersmissen, S. V. Huylenbroeck, H. Struyf, Tetsu Tanaka

引用次数: 2

Manufacturing and test assistance for 3D-Integrated heterogeneous systems 制造和测试协助3d集成异构系统

2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152171

A. Grünewald, M. Wahl, R. Brück

引用次数: 0