Thermal challenges for heterogeneous 3D ICs and opportunities for air gap thermal isolation

Abstract

Thermal crosstalk within a heterogeneous 3D IC results in higher temperatures for low-power dice; this is particularly true in memory-logic, photonic-logic, and MEMS-logic stacks. The elevated temperatures may consequently impact the performance of the low-power devices. This paper describes a thermal solution for both heat removal as well as thermal isolation within a 3D chip stack. Based on the evaluated memory-logic 3D architecture and compared to conventional air-cooling, the proposed technologies reduce the maximum temperature of the memory die from 75.6 °C to 36.7 °C and processor die from 75.9 °C to 60.1 °C.