Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation

Abstract

In this study, we propose a three-dimensional (3D) interconnect network implementation based on a modified Mesh-of-Clusters (MoC) topology for FPGA architecture design. Design and experimental setup is developed to demonstrate the improvement in performance, power and area of 2.5D and 3D MoC-based FPGA architecture. MoC starts with a mesh of nodes and builds a separate hierarchical network along each row and column in the mesh. To obtain the optimal MoC programmable interconnect structure with high performance and density, the routing architecture of the 2D MoC-based FPGA is modified to include long routing segments which span multiple switch blocks in every row and column. By adjusting the percentage of long wire and span, we can design and build 2.5D and 3D high density MoC FPGAs. To design 3D MoC-based FPGAs, we cut the 2D MoC FPGA into two equal FPGA dies and we adjust the long wire span factor to connect the two dies. Then, these long wire segments are converted as 3D through silicon via (TSV) technology. To design 2.5D interposer based multi-FPGA architecture, we use the same principle of cuts and we adjust the long wires span to remain within die connections. However, we apply constraints at cutline location to reduce the die to die interposer connections. A 3D physical design CAD for MoC-based FPGA is developed using Global Foundries 130nm technology node modified to use TSV designs from Tezzaron Semiconductor inc. Using our 3D design and simulation tool flow developed for MoC-based FPGA, we demonstrate that the speed, power and area of 3D MoC-based FPGA architecture are improved respectively by 35%, 21% and 47% in comparison to 2D MoC-based FPGA.