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Electroless metal deposition for IC and TSV applications 用于IC和TSV应用的化学金属沉积
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152175
J. Rohan, D. Casey, Monika Zygowska, Michael Moore, Brian Shanahan
{"title":"Electroless metal deposition for IC and TSV applications","authors":"J. Rohan, D. Casey, Monika Zygowska, Michael Moore, Brian Shanahan","doi":"10.1109/3DIC.2014.7152175","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152175","url":null,"abstract":"Ultrathin film electroless deposition of Cu and Ni is shown for IC and TSV barrier layer / interconnect applications as an alternative to vacuum based deposition techniques. Cu films of approximately 20 nm were achieved while coherent electroless Ni can be deposited to single digit nm levels. The use of self-assembled monolayers facilitates electroless deposition in high aspect ratio structures. This activation process in combination with ultrathin film barrier/seed layer deposition by electroless processing enables scaling for both IC and TSV interconnect applications.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129392103","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling of substrate contacts in TSV-based 3D ICs 基于tsv的三维集成电路中衬底触点的建模
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152178
Masayuki Watanabe, M. Fukase, Masashi Imai, N. Niioka, Tetsuya Kobayashi, Rosely Karel, A. Kurokawa
{"title":"Modeling of substrate contacts in TSV-based 3D ICs","authors":"Masayuki Watanabe, M. Fukase, Masashi Imai, N. Niioka, Tetsuya Kobayashi, Rosely Karel, A. Kurokawa","doi":"10.1109/3DIC.2014.7152178","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152178","url":null,"abstract":"This paper proposes closed-form expressions of parasitic parameters in a silicon substrate that consider substrate contacts. In general bulk CMOS technologies, the standard cells with bulk (substrate and well) contacts or tap cells for bulk contacts are used in physical layout designs. As tap cell placement methods, there are dense random placements and sparse regular placements in cell rows vertically. We call the former the fine-grained substrate contacts and the latter the coarse-grained ones. First, their structures are modeled for simplification, and then the equivalent circuit model is presented. Next, closed-form expressions of parasitic parameters for TSV-to-TSVs and TSV-to-contacts are proposed. Finally, validity of the proposed method is discussed. The proposed expressions agree with 3D electromagnetic field solvers with reasonable accuracy. When an enormous amount of TSVs are placed regularly, designers can extract parasitic parameters quickly.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121368972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Simple and low cost technique for stacking known good dies to create compact 3D stacked parallel optics assemblies 简单和低成本的技术，堆叠已知的好模具，以创建紧凑的3D堆叠平行光学组件
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152155
O. Raz, P. Duan, H. Dorren
{"title":"Simple and low cost technique for stacking known good dies to create compact 3D stacked parallel optics assemblies","authors":"O. Raz, P. Duan, H. Dorren","doi":"10.1109/3DIC.2014.7152155","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152155","url":null,"abstract":"We demonstrate a method for stacking and connecting KGD on each other. The method requires no pre-processing of the ICs and die placement can be done using standard pick and place machines. This novel process allows creating >200um high lithographically defined interconnects and is a simple, scalable and low cost alternative to other techniques for interconnecting 3D stacked ICs.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127800901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Conventional magnetron sputtering of metal seed layers on high aspect ratio vias with tilting 传统磁控溅射的金属种子层在高纵横比孔倾斜
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152169
Y. Song, Yunho Han, T. Yim
{"title":"Conventional magnetron sputtering of metal seed layers on high aspect ratio vias with tilting","authors":"Y. Song, Yunho Han, T. Yim","doi":"10.1109/3DIC.2014.7152169","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152169","url":null,"abstract":"3D ICs involve interconnected ICs as they contact each other by means of through-silicon-vias (TSVs). Although it is a cheap process and suitable to mass production, the conventional sputtering method has not been widely used to fabricate high aspect ratio vias due to its more or less rectilinear propagation property. In this study, the effect of sputtering conditions on the growth mechanism of seed layers was investigated to fabricate 10:1 or higher aspect ratio TSVs through the conventional sputtering method. In order to improve the quality of Cu seed layers, a Mo buffer layer was pre-deposited because Mo has a good conductivity and an intermediate thermal expansion coefficient between Si and Cu. To obtain a homogeneous and continuous Cu/Mo layers on TSV, the effect of sputtering conditions and substrate tilting was examined. Cu/Mo seed layers with low electrical resistivity of 2.07 microohm centimeters were obtained when the sputtering target power was maintained 5 kW, 0.67 Pa, and with 500W bias. The film stress was tensile in the sputter pressure of 0.67 Pa but close to compressive in the 0.13 Pa conditions.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123968174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
3D-enabled customizable embedded computer (3DECC) 可定制的3d嵌入式计算机(3DECC)
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152143
P. Franzon, E. Rotenberg, James Tuck, Huiyang Zhou, W. R. Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, S. Lipa, C. Li, Jong Beom Park, J. Schabel
{"title":"3D-enabled customizable embedded computer (3DECC)","authors":"P. Franzon, E. Rotenberg, James Tuck, Huiyang Zhou, W. R. Davis, Hongwen Dai, Joonmoo Huh, Sungkwan Ku, S. Lipa, C. Li, Jong Beom Park, J. Schabel","doi":"10.1109/3DIC.2014.7152143","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152143","url":null,"abstract":"This paper describes a 3D computer architecture designed to achieve the lowest possible power consumption for “embedded applications” like radar and signal processing. It introduces several unique concepts including a low-power SIMD tile, low-power 3D memories, and 3D and 2.5D interconnect that is circuit switched so it can be tuned at run-time for a specific application. When conservatively projected to the 7 nm node, simulations of the architecture show potential for exceeding 75 GFLOPS/W, about 20x better than today's CPUs and GPUs. This translates to 13 pJ/FLOP. This paper will focus on the 3D specific aspects of the design. This architecture is highly suited to DSP and multimedia workflows.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123714714","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges 3D堆叠IC与3D中间体集成的比较研究:加工与组装挑战
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152146
J. D. Vos, V. Cherman, M. Detalle, Teng Wang, A. Salahouelhadj, R. Daily, G. V. D. Plas, E. Beyne
{"title":"Comparative study of 3D stacked IC and 3D interposer integration: Processing and assembly challenges","authors":"J. D. Vos, V. Cherman, M. Detalle, Teng Wang, A. Salahouelhadj, R. Daily, G. V. D. Plas, E. Beyne","doi":"10.1109/3DIC.2014.7152146","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152146","url":null,"abstract":"3D stacked IC (SIC) vs. 3D Interposer wafer processing and assembly challenges are discussed in this paper. We report on the key enabling technologies like wafer thinning, thin wafer handling, TSV, micro bumping, package bumping, stacking and packaging. The limited micro bump yield loss in the 3D SIC case is explained by modeling of bonding force distribution. It is also shown that for sequential stacking a NiB cap of the Cu micro bumps is heavily increasing stacking yield.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"82 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129959731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Advanced processing for high efficiency inductors for 2.5D/3D Power Supply in Package 封装2.5D/3D电源高效电感的先进工艺
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152183
R. Anthony, S. Kulkarni, Ningning Wang, S. O'Mathuna
{"title":"Advanced processing for high efficiency inductors for 2.5D/3D Power Supply in Package","authors":"R. Anthony, S. Kulkarni, Ningning Wang, S. O'Mathuna","doi":"10.1109/3DIC.2014.7152183","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152183","url":null,"abstract":"Realizing an integrated Power Supply in Package solution using a 2.5D or 3D integration technology requires significant advancement in manufacturing processes of magnetic components such as inductors, transformer. Development of these integrated structures involves fabrication of high aspect ratio integrated windings and 3D core topology. These process improvements are required to reduce the losses i.e, copper conduction loss and enhance inductance density through a multilayer closed magnetic core. This work reports development of resist processing techniques to achieve thick copper windings with resist aspect ratio of 5.5. Integrated inductors and transformers require closed magnetic cores such as (Ni45Fe55) to maximize the stored flux. At higher operational frequencies, the lower device footprint requires stacked multi-layer magnetic cores with 3D topologies to close the flux path. This work also presents new processing technique using temporary resist to pattern magnetic core deposited in a cavity of over 70 μm depth while minimizing the over-etch of the magnetic core. A 75 μm single spin process is developed with negative tone THB-151N as replacement for existing permanent SU-8 resist process. This process has significant advantage in terms of easy removal, resolution and adhesion to metals for electroplating applications. Core over-etch were reduced by 44% on using THB 151N and excellent adhesion was achieved.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121512967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Fault detection and isolation of multiple defects in through silicon via (TSV) channel 硅通孔(TSV)通道多缺陷故障检测与隔离
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152170
D. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi
{"title":"Fault detection and isolation of multiple defects in through silicon via (TSV) channel","authors":"D. Jung, Heegon Kim, Jonghoon J. Kim, Sukjin Kim, Joungho Kim, Hyun-Cheol Bae, Kwang-Seong Choi","doi":"10.1109/3DIC.2014.7152170","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152170","url":null,"abstract":"Through silicon via (TSV) based 3D-IC is the key technology to satisfy the continuously growing demand on lower power consumption, higher system bandwidth and smaller form factor of electronic devices. As the I/O count increases up to the order of tens of thousands for high speed data transmission, TSV diameter and interconnection pitch are reduced, which may cause various defects throughout the channel. In this paper, we present a fault detection and isolation method for multiple defects in TSV channel by analyzing the electrical characteristics in frequency- and time-domain. In TSV channels with 5-layer stacked dies, open and short defects are intentionally inserted in different locations and the electrical characteristics are analyzed by 3D FEM solver simulation. The type of defects can be distinguished by S21 magnitude; by comparing S11 and S22 magnitude curves, the location of defects can be localized.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128887259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits InP / GaN / Si异构集成电路中异质互连的热效应
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152182
T. R. Harris, P. Franzon, W. R. Davis, Lee Wang
{"title":"Thermal effects of heterogeneous interconnects on InP / GaN / Si diverse integrated circuits","authors":"T. R. Harris, P. Franzon, W. R. Davis, Lee Wang","doi":"10.1109/3DIC.2014.7152182","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152182","url":null,"abstract":"The DAPRA Diverse Accessible Heterogeneous Integration (DAHI) initiative seeks to build capability in production of integrated semiconductor circuits of differing materials. Integration of materials such as GaN, InP, SiGe, and Si is a natural extension of the 3D-IC perspective and provides a unique solution for high performance circuits. In this approach, application of a component is no longer dependent on semiconductor material selection. In this paper, preliminary results are presented which examine the thermal performance of the technology. A thermal analysis prototype solution in Mentor Graphics® Calibre® provides surface heat maps based on IC layout, material property, and geometric configuration files. Chiplets are connected by heterogeneous interconnect (HIC). Differences in thermal performance of GaN and InP chiplets are explored by varying the number of HICs. Two methods for building up the model of a test chip are compared. One method automatically places discrete blocks in the model to represent HICs, while the other uses thermal material properties extracted from the layout.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128454782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration 铜填充TSV形成与聚苯乙烯- ht绝缘体低温兼容3D集成
2014 International 3D Systems Integration Conference (3DIC) Pub Date : 2014-12-01 DOI: 10.1109/3DIC.2014.7152162
B. T. Tung, Xiaojin Cheng, N. Watanabe, F. Kato, K. Kikuchi, M. Aoyagi
{"title":"Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration","authors":"B. T. Tung, Xiaojin Cheng, N. Watanabe, F. Kato, K. Kikuchi, M. Aoyagi","doi":"10.1109/3DIC.2014.7152162","DOIUrl":"https://doi.org/10.1109/3DIC.2014.7152162","url":null,"abstract":"In this paper, investigation of Parylene-HT for using as insulation/liner in through-silicon-via (TSV) is presented. Bottom-up copper filled TSVs with 1 μm Parylene-HT insulator with aspect ratios (ARs) up to 10, are demonstrated on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and copper electroplating processes. Cross sectional inspections on the fabricated TSVs confirm the pin-hole free, high-uniformity, good conformal coverage room temperature deposited Parylene-HT liner, the void- and seam-free filled Cu, as well as the low diffusivity of Cu into Parylene-HT. Excellent insulation function of Parylene-HT liner, i.e., capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm2 at a field of 0.25 MV/cm, were also confirmed on the fabricated TSV. As the Parylene-HT deposition and Cu electroplating processes can be implemented at room temperature, the copper filled TSV formation with Parylene-HT insulator investigated in this work is highly compatible with low-temperature 3D integration.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"261 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131899043","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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