J. Rohan, D. Casey, Monika Zygowska, Michael Moore, Brian Shanahan
{"title":"Electroless metal deposition for IC and TSV applications","authors":"J. Rohan, D. Casey, Monika Zygowska, Michael Moore, Brian Shanahan","doi":"10.1109/3DIC.2014.7152175","DOIUrl":null,"url":null,"abstract":"Ultrathin film electroless deposition of Cu and Ni is shown for IC and TSV barrier layer / interconnect applications as an alternative to vacuum based deposition techniques. Cu films of approximately 20 nm were achieved while coherent electroless Ni can be deposited to single digit nm levels. The use of self-assembled monolayers facilitates electroless deposition in high aspect ratio structures. This activation process in combination with ultrathin film barrier/seed layer deposition by electroless processing enables scaling for both IC and TSV interconnect applications.","PeriodicalId":231905,"journal":{"name":"2014 International 3D Systems Integration Conference (3DIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International 3D Systems Integration Conference (3DIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/3DIC.2014.7152175","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
Ultrathin film electroless deposition of Cu and Ni is shown for IC and TSV barrier layer / interconnect applications as an alternative to vacuum based deposition techniques. Cu films of approximately 20 nm were achieved while coherent electroless Ni can be deposited to single digit nm levels. The use of self-assembled monolayers facilitates electroless deposition in high aspect ratio structures. This activation process in combination with ultrathin film barrier/seed layer deposition by electroless processing enables scaling for both IC and TSV interconnect applications.