Copper filled TSV formation with Parylene-HT insulator for low-temperature compatible 3D integration

Abstract

In this paper, investigation of Parylene-HT for using as insulation/liner in through-silicon-via (TSV) is presented. Bottom-up copper filled TSVs with 1 μm Parylene-HT insulator with aspect ratios (ARs) up to 10, are demonstrated on a 100 μm-thick Si wafer through via etching, parylene vapor deposition, and copper electroplating processes. Cross sectional inspections on the fabricated TSVs confirm the pin-hole free, high-uniformity, good conformal coverage room temperature deposited Parylene-HT liner, the void- and seam-free filled Cu, as well as the low diffusivity of Cu into Parylene-HT. Excellent insulation function of Parylene-HT liner, i.e., capacitance of 0.164 pF/TSV and leakage current density of 22 pA/cm2 at a field of 0.25 MV/cm, were also confirmed on the fabricated TSV. As the Parylene-HT deposition and Cu electroplating processes can be implemented at room temperature, the copper filled TSV formation with Parylene-HT insulator investigated in this work is highly compatible with low-temperature 3D integration.