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2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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New Locos Trench Oxide IGBT Enables 25% Higher Current Density in 4.5kV/1500A Module 新型Locos沟槽氧化物IGBT在4.5kV/1500A模块中使电流密度提高25%
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757651
L. Ngwendson, I. Deviny, C. Zhu, I. Saddiqui, J. Hutchings, C. Kong, Y. Wang, H. Luo
{"title":"New Locos Trench Oxide IGBT Enables 25% Higher Current Density in 4.5kV/1500A Module","authors":"L. Ngwendson, I. Deviny, C. Zhu, I. Saddiqui, J. Hutchings, C. Kong, Y. Wang, H. Luo","doi":"10.1109/ISPSD.2019.8757651","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757651","url":null,"abstract":"In this paper we present first results of a 4.5kV/1500A IGBT module using new LOCOS (Local Oxidation of Silicon) Trench Oxide IGBTs (LTO-IGBT). It is shown that this new module with increased current density compared to the previous DMOS generation, also show very robust dynamic and competitive performance at $mathbf{T}_{mathbf{J}}=150^{0}mathbf{C}$.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116304157","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Breakthrough in Channel Mobility Limit of Nitrided Gate Insulator for SiC DMOSFET with Novel High-temperature N2 Annealing 用新型高温N2退火技术突破SiC DMOSFET氮化栅绝缘子通道迁移率极限
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757649
S. Asaba, T. Ito, S. Fukatsu, Y. Nakabayashi, T. Shimizu, M. Furukawa, T. Suzuki, R. Iijima
{"title":"Breakthrough in Channel Mobility Limit of Nitrided Gate Insulator for SiC DMOSFET with Novel High-temperature N2 Annealing","authors":"S. Asaba, T. Ito, S. Fukatsu, Y. Nakabayashi, T. Shimizu, M. Furukawa, T. Suzuki, R. Iijima","doi":"10.1109/ISPSD.2019.8757649","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757649","url":null,"abstract":"We have improved the limited channel mobility of nitridation on silicon carbide Si-face planar MOSFET to 50 cm2/Vs with the newly developed gate insulator process. Using the novel high-temperature N2 annealing process, nitrogen whose density is twice that of the nitrogen used in the conventional NOX process can be introduced to the MOS interface. The developed N2 annealing is applied to a 1.2 kV class vertical MOSFET and remarkable reduction of the on-resistance has been demonstrated.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125255743","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
New Circuit Topology for System-Level Reliability of GaN GaN系统级可靠性的新电路拓扑
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757683
Ming-Cheng Lin, Wen-Che Chang, Haw-Yun Wu, G. Lansbergen, M. Kwan, J. Yu, Cheng-Pao Wu, C. Tsai, H. Tuan, A. Kalnitsky
{"title":"New Circuit Topology for System-Level Reliability of GaN","authors":"Ming-Cheng Lin, Wen-Che Chang, Haw-Yun Wu, G. Lansbergen, M. Kwan, J. Yu, Cheng-Pao Wu, C. Tsai, H. Tuan, A. Kalnitsky","doi":"10.1109/ISPSD.2019.8757683","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757683","url":null,"abstract":"To accelerate GaN adoption, beyond-JEDEC system-level reliability should be done to prove the robustness of GaN in applications. In this paper, a new hard switching test vehicle (half-bridge RC load) was proposed & demonstrated to achieve system-like stress, flexibility of acceleration test, low system power consumption with large sample size, easy setup & control which can meet system-level reliability requirement.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124666423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 12
Feasibility and Limitation of DC/DC Multilevel Converter Power ICs Using Standard CMOS Transistors 采用标准CMOS晶体管的DC/DC多电平变换器功率集成电路的可行性与局限性
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757654
Runtao Ning, Yuanfeng Zhou, A. Kundu, Z. Shen
{"title":"Feasibility and Limitation of DC/DC Multilevel Converter Power ICs Using Standard CMOS Transistors","authors":"Runtao Ning, Yuanfeng Zhou, A. Kundu, Z. Shen","doi":"10.1109/ISPSD.2019.8757654","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757654","url":null,"abstract":"This paper investigates the feasibility and limitation of designing DC/DC converter power ICs using standard CMOS technology. Comparing to custom BCDMOS technologies, this path leads to lower cost and shorter development cycle time, benefiting from the high volume CMOS manufacturing ecosystem. Our study indicates that the flying capacitor multilevel converter (FCMC) topology can facilitate DC/DC conversion using standard CMOS transistors for an input voltage up to 15V for the 90nm/65nm CMOS nodes, and 12V for the 45nm CMOS node. The CMOS FCMC solution offers a much lower switching loss than the common buck converters using LDMOS transistors derived from the same CMOS platform. TCAD and IC circuit simulation are extensively used to explore this design concept for the case of a 7.5V to 1.5V 50MHz converter. The calculated power loss and MOSFET performance FOM are compared between the two solutions. A PCB level FCMC prototype using discrete low voltage MOSFETs is built and tested to validate this concept in lieu of a CMOS chip prototype. The physical limitation of this technical approach is also analyzed with extensive TCAD simulation.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116537430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Influence of Carrier Lifetime on Silicon Carbide Power Devices for Pulsed Power Application 载流子寿命对脉冲功率碳化硅功率器件的影响
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757643
K. Zhou, Yingxin Cui, Lianghui Li, Yunfei Gu, Lin Zhang, Shuairong Deng, Zhiqiang Li, Jun-tao Li
{"title":"Influence of Carrier Lifetime on Silicon Carbide Power Devices for Pulsed Power Application","authors":"K. Zhou, Yingxin Cui, Lianghui Li, Yunfei Gu, Lin Zhang, Shuairong Deng, Zhiqiang Li, Jun-tao Li","doi":"10.1109/ISPSD.2019.8757643","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757643","url":null,"abstract":"In this paper, we investigate the influence of carrier lifetime on SiC GTO and PiN devices for pulsed power application. Both the device characteristics and the circuit dynamic performance in pulsed discharging system are studied based on simulation and experiments. The influence of $boldsymbol{tau}_{mathbf{HL}}$ on the static and dynamic discharging characteristics in both single- and multi-stage pulsed power network (PFN) are analyzed by extensive mix-mode simulation considering thermoelectric effect within SiC devices. Simulation results show that the SiC GTO is more sensitive to carrier lifetime and induces the power dissipation 10X higher than that of SiC PiN during pulsed discharging. The discharging capability of SiC GTO decreases for $boldsymbol{tau}_{mathbf{HL}} < 0.4 boldsymbol{mu}mathbf{s}$. The heat generates in the drift region and tends to shift towards the top anode region in long pulse width discharging. The simulation is demonstrated by experimental data of our fabricated SiC GTOs.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116578334","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Broadband TCAD mixed-mode simulation framework for predictive modeling of fast dynamic switching events 用于快速动态切换事件预测建模的宽带TCAD混合模式仿真框架
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757578
D. Popescu, Maximilian Treiber
{"title":"Broadband TCAD mixed-mode simulation framework for predictive modeling of fast dynamic switching events","authors":"D. Popescu, Maximilian Treiber","doi":"10.1109/ISPSD.2019.8757578","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757578","url":null,"abstract":"In this paper, we develop a simulation framework for analyzing and optimizing the large signal, dynamic switching behavior of power devices. This framework enables us to use TCAD models of our active devices, together with a broadband description of the application board. All elements are coupled through a mixed-mode SPICE instance. Simulated results, obtained with this new method for two application boards, are compared to measurement data and their agreement is analyzed.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133740611","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Vertical 1.2kV SiC Power MOSFETs with High-k/Metal Gate Stack 垂直1.2kV SiC功率mosfet，高k/金属栅极堆叠
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757601
S. Wirths, Y. Arango, A. Prasmusinto, G. Alfieri, E. Bianda, A. Mihaila, L. Kranz, M. Bellini, L. Knoll
{"title":"Vertical 1.2kV SiC Power MOSFETs with High-k/Metal Gate Stack","authors":"S. Wirths, Y. Arango, A. Prasmusinto, G. Alfieri, E. Bianda, A. Mihaila, L. Kranz, M. Bellini, L. Knoll","doi":"10.1109/ISPSD.2019.8757601","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757601","url":null,"abstract":"We demonstrate the first integration of high-k/metal gate stacks in vertical 1.2kV SiC power MOSFETs including static and dynamic characterization as well as safe operation area (SOA). The high-k/4H-SiC MOS interface exhibits a remarkably low interface defect state density and improved threshold voltage stability compared to conventional gate stacks based on SiO2. Moreover, we achieved an impressive performance boost in terms of on-resistance due to this low-defective interface and increased gate capacitance. Compared to vertical devices with SiO2/poly Si gate stacks these devices exhibit a negligible hysteresis.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116377140","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Planar 1.2kV SiC MOSFETs with retrograde channel profile for enhanced ruggedness 平面1.2kV SiC mosfet，具有逆行沟道轮廓，增强坚固性
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757648
L. Knoll, A. Mihaila, S. Wirths, Y. Arango, A. Prasmusinto, E. Bianda, L. Kranz, M. Bellini, G. Romano, C. Papadopoulos
{"title":"Planar 1.2kV SiC MOSFETs with retrograde channel profile for enhanced ruggedness","authors":"L. Knoll, A. Mihaila, S. Wirths, Y. Arango, A. Prasmusinto, E. Bianda, L. Kranz, M. Bellini, G. Romano, C. Papadopoulos","doi":"10.1109/ISPSD.2019.8757648","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757648","url":null,"abstract":"The static and dynamic performance of Silicon Carbide (SiC) MOSFET rated for 1200V applications has been investigated. MOSFETs with a planar design and several different cell pitches have been fabricated. Special attention has been dedicated to the channel design, where a novel retrograde doping profile has been employed. For reference, a more common box profile channel has also been used. Turn-off measurements under high current and over voltage conditions reveal that the MOSFET body diode offers wide safe operating area capability. The MOSFETs feature exceptional ruggedness against long short circuit events, with the retrograde channel designs able to withstand the $10boldsymbol{mu} mathbf{s}$ industry standard specification.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133048256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Switching Loss Model of SiC MOSFET Promoting High Frequency Applications 促进高频应用的SiC MOSFET开关损耗模型
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757669
Xuan Li, Xu Li, Liping Yang, A. Huang, Pengkun Liu, Xiaochuan Deng, Bo Zhang
{"title":"Switching Loss Model of SiC MOSFET Promoting High Frequency Applications","authors":"Xuan Li, Xu Li, Liping Yang, A. Huang, Pengkun Liu, Xiaochuan Deng, Bo Zhang","doi":"10.1109/ISPSD.2019.8757669","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757669","url":null,"abstract":"In this work, the influence of parasitic capacitance on the switching loss of SiC MOSFET is investigated. The switching loss models considering $boldsymbol{C}_{mathbf{gd}}$ and $boldsymbol{C}_{mathbf{ds}}$ are obtained. Furthermore, the intrinsic minimum switching loss is identified as the energy dissipation resulting from the parasitic capacitance of the SiC MOSFET. Finally, the intrinsic losses of a number of commercial SiC MOSFETs are compared using the proposed model.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134290046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
1.6 kV Vertical Ga2O3 FinFETs With Source-Connected Field Plates and Normally-off Operation 具有源连接场极板和常关工作的1.6 kV垂直Ga2O3 finfet
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757633
Zongyang Hu, K. Nomoto, Wenshen Li, R. Jinno, Tohru Nakamura, D. Jena, H. Xing
{"title":"1.6 kV Vertical Ga2O3 FinFETs With Source-Connected Field Plates and Normally-off Operation","authors":"Zongyang Hu, K. Nomoto, Wenshen Li, R. Jinno, Tohru Nakamura, D. Jena, H. Xing","doi":"10.1109/ISPSD.2019.8757633","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757633","url":null,"abstract":"High performance Ga2O3 vertical FinFETs with a breakdown voltage of 1.6 kV, a drain current density of 600 A/cm2 have been demonstrated in this work. Fin-shaped channels with sub-micron widths lead to a high threshold voltage of 4 V, and also provide strong RESURF effects to reduce the drain leakage current and increase the breakdown voltage. A low leakage current of lower than 10−3 A/cm2 is maintained until the hard breakdown of the transistor. In order to sustain high voltage, a source-connected field plate (FP) supported by a dielectric layer is implemented at the outer edge of the gate pad as the edge termination, which enabled a breakdown voltage almost 2 times as high as those without FP. Device simulation shows that the highest electric field peak appears at the FP edge, which suggests further improvement of the breakdown voltage is possible by optimizing the FP design or implementing additional edge terminations.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132379006","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
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