Vertical 1.2kV SiC Power MOSFETs with High-k/Metal Gate Stack

Abstract

We demonstrate the first integration of high-k/metal gate stacks in vertical 1.2kV SiC power MOSFETs including static and dynamic characterization as well as safe operation area (SOA). The high-k/4H-SiC MOS interface exhibits a remarkably low interface defect state density and improved threshold voltage stability compared to conventional gate stacks based on SiO2. Moreover, we achieved an impressive performance boost in terms of on-resistance due to this low-defective interface and increased gate capacitance. Compared to vertical devices with SiO2/poly Si gate stacks these devices exhibit a negligible hysteresis.