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2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

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Analysis of Degradation Phenomena in Bipolar Degradation Screening Process for SiC-MOSFETs sic - mosfet双极降解筛选过程中降解现象分析
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757598
T. Ishigaki, T. Murata, K. Kinoshita, T. Morikawa, T. Oda, R. Fujita, K. Konishi, Y. Mori, A. Shima
{"title":"Analysis of Degradation Phenomena in Bipolar Degradation Screening Process for SiC-MOSFETs","authors":"T. Ishigaki, T. Murata, K. Kinoshita, T. Morikawa, T. Oda, R. Fujita, K. Konishi, Y. Mori, A. Shima","doi":"10.1109/ISPSD.2019.8757598","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757598","url":null,"abstract":"We have developed a 3.3 kV ultra-high power density SiC power module, which was realized by fulfilment with only SiC-MOSFETs. As a countermeasure for bipolar degradation issues related to body diodes in the MOSFET structure, a high throughput screening process has been introduced. In the screening process, over 10000 chips of 3.3 kV SiC-MOSFET were evaluated. The large amount of data firstly reveals the probability distribution of the degradation phenomena and enables us to study the relationship with defect densities of the state-of-the-art SiC wafers. Furthermore, origins of the degradation were investigated by teardown analysis. The degradation is caused by the expansion or generation of bar-shaped stacking faults. It was identified that their origins are pre-existing bar-shaped stacking faults in a SiC epi-layer, a basal plane dislocation in a SiC substrate, or a closed micropipe.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132456652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 29
100 A Vertical GaN Trench MOSFETs with a Current Distribution Layer 带电流分布层的100a垂直GaN沟槽mosfet
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757621
T. Oka, T. Ina, Y. Ueno, J. Nishii
{"title":"100 A Vertical GaN Trench MOSFETs with a Current Distribution Layer","authors":"T. Oka, T. Ina, Y. Ueno, J. Nishii","doi":"10.1109/ISPSD.2019.8757621","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757621","url":null,"abstract":"This paper reports on vertical GaN-based trench MOSFETs operating at 100 A for the first time. A current distribution layer (CDL) in a drift layer is employed for the high current operation. An effective insert position of the CDL is designed and, thereby, the current density of the MOSFET with the CDL is increased about 1.17 times higher than that of the MOSFET without the CDL. Large MOSFET chips with a drain current of up to 100 A are fabricated and their switching characteristics are demonstrated.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"7 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133205457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
Self-sustained Oscillation of Superjunction MOSFET Intrinsic Diode During Reverse Recovery Transient 反向恢复瞬态过程中超结MOSFET本征二极管的自持续振荡
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757579
Peng Xue, L. Maresca, M. Riccio, G. Breglio, A. Irace
{"title":"Self-sustained Oscillation of Superjunction MOSFET Intrinsic Diode During Reverse Recovery Transient","authors":"Peng Xue, L. Maresca, M. Riccio, G. Breglio, A. Irace","doi":"10.1109/ISPSD.2019.8757579","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757579","url":null,"abstract":"In this paper, the self-sustained oscillation occurs on the reverse recovery transient of the superjunction MOSFET intrinsic diode is studied. Based on the double-pulse test, the characteristics of the self-sustained oscillation is identified. Utilizing the Senturus TCAD simulation, the superjunction MOSFET intrinsic diode's reverse recovery oscillation behavior is reproduced. By analyzing the oscillation waveforms, the positive feedback mechanism which excites the oscillation is revealed at the end of the paper.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"193 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115426367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Investigations of p-Shielded SiC Trench IGBT with Considerations on IE Effect, Oxide Protection and Dynamic Degradation 考虑IE效应、氧化保护和动态降解的p屏蔽SiC沟槽IGBT研究
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757642
Jin Wei, Meng Zhang, Huaping Jiang, Baikui Li, Zheyang Zheng, K. J. Chen
{"title":"Investigations of p-Shielded SiC Trench IGBT with Considerations on IE Effect, Oxide Protection and Dynamic Degradation","authors":"Jin Wei, Meng Zhang, Huaping Jiang, Baikui Li, Zheyang Zheng, K. J. Chen","doi":"10.1109/ISPSD.2019.8757642","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757642","url":null,"abstract":"This work investigates the design of gate structure for the SiC trench IGBTs. The conventional trench IGBT structure established in silicon is not suitable for SiC IGBT, since it suffers from high oxide field. The grounded p-shield concept developed for SiC trench MOSFET cannot be readily transferred to SiC trench IGBT, since it counteracts the injection enhancement (IE) effect and nullifies the purpose of a trench gate structure. The floating p-shield structure has been found to cause severe dynamic degradation in SiC trench MOSFETs due to the charge storage effect. However, this dynamic degradation is effectively suppressed in the SiC trench IGBT, since the holes injected from the collector neutralize the stored negative charges in the floating p-shield. In the meanwhile, the floating p-shield is found to effectively suppress the high oxide field while maintains the IE effect. Thus, the floating p-shield solves the key issues and proves a promising solution for SiC trench IGBTs.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124132333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Analysis the complex tradeoff among Eon-VCEsat-SCSOA and EMI noise through the single chip evaluation method 通过单芯片评估方法，分析了Eon-VCEsat-SCSOA与EMI噪声之间的复杂权衡
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757663
K. Nishi, Tetsuo Takahashi, A. Narazaki
{"title":"Analysis the complex tradeoff among Eon-VCEsat-SCSOA and EMI noise through the single chip evaluation method","authors":"K. Nishi, Tetsuo Takahashi, A. Narazaki","doi":"10.1109/ISPSD.2019.8757663","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757663","url":null,"abstract":"As a compensation for the superior VCEsat, Carrier Stored Trench gate Bipolar Transistor (CSTBT™) has the more complex tradeoff among Eon-VCEsat-SCSOA and EMI noise compared to IGBT. EMI noise evaluation is known to need special facilities such as a shield room and antenna detector, which deteriorates an evaluation efficiency and consistency. We found that EMI noise can be indirectly but simply and accurately evaluated by using the surge current under small current turn-on of single-chip IGBTs without any EMI shield facilities. By using this method, maintaining the CSTBT's better tradeoff among Eon-VCEsat-SCSOA, we have succeeded to reduce the EMI noise by decreasing Carrier Stored Layer doping concentration and/or gate-collector capacitance while adjusting channel density.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128509897","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Time-Resolved Short Circuit Failure Analysis of SiC MOSFETs SiC mosfet的时间分辨短路失效分析
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757564
T. Ziemann, A. Tsibizov, Bhagyalakshmi Kakarla, L. Bort, U. Grossner
{"title":"Time-Resolved Short Circuit Failure Analysis of SiC MOSFETs","authors":"T. Ziemann, A. Tsibizov, Bhagyalakshmi Kakarla, L. Bort, U. Grossner","doi":"10.1109/ISPSD.2019.8757564","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757564","url":null,"abstract":"High-speed optical imaging is used in conjunction with fast electrical measurements to advance the understanding of the development of short circuit failures in silicon carbide power MOSFETs. Special samples are manufactured, which are compatible and comparable to TO-247 packages, but do not have any encapsulation. This allows optical observation of die surface during the test. The information on visible processes on the die allows for a better understanding of the sequence of events leading up to a failure. Imagery of destructive drain-source failures is also obtained, as well as post-failure images of surface and cross-sections. Aluminum metal melting is observed even for very short tests, before electrical indications of damage. The onset and completion of melting are used as information on the temperature of the die surface. Using this data for calibration, a detailed electro-thermal model is then used to simulate the temperature distribution and evolution during the short circuit.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"547 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127050895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Silicon RC-Snubber for 900 V Applications Utilising non-Stoichiometric Silicon Nitride 硅rc缓冲器用于900 V应用，利用非化学计量氮化硅
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757589
N. Boettcher, T. Heckel, T. Erlbacher, K. Pelaic
{"title":"Silicon RC-Snubber for 900 V Applications Utilising non-Stoichiometric Silicon Nitride","authors":"N. Boettcher, T. Heckel, T. Erlbacher, K. Pelaic","doi":"10.1109/ISPSD.2019.8757589","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757589","url":null,"abstract":"This paper presents a novel approach for the realisation of silicon RC-snubbers suitable for 900 V applications. The fabrication of dielectric layers with a thickness feasible for this voltage class poses challenges in terms of mechanical stress management, which have not been overcome by other approaches so far. The presented technology focuses on stress reduction during fabrication by utilisation of non-stoichiometric silicon nitride. A wide case study is performed in order to characterise dielectric layer stacks including non-stoichiometric silicon nitride with respect to manufacturability and electric properties. By keeping the amount of non-stoichiometric silicon nitride in dielectric layer stack small, silicon RC-snubbers exhibiting dielectric strength of more than 1500 V and leakage current of less than 100 nA at 900 V can be fabricated. The feasibility for 900 V switching application is demonstrated in a double-pulse experiment.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126897837","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Development of GaN Power IC Platform and All GaN DC-DC Buck Converter IC GaN功率IC平台及全GaN DC-DC降压变换器IC的开发
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757674
Ruize Sun, Y. C. Liang, Y. Yeo, Cezhou Zhao, Wanjun Chen, Bo Zhang
{"title":"Development of GaN Power IC Platform and All GaN DC-DC Buck Converter IC","authors":"Ruize Sun, Y. C. Liang, Y. Yeo, Cezhou Zhao, Wanjun Chen, Bo Zhang","doi":"10.1109/ISPSD.2019.8757674","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757674","url":null,"abstract":"In this paper, the GaN power IC platform is developed based on Au-free AlGaN/GaN MIS-HEMTs and a constant-output-ripple all GaN DC-DC buck converter IC is firstly realized with integrated gate driver, pulse width modulation (PWM) feedback control and over-current protection (OCP) circuits. The fabricated all GaN integrated DC-DC buck converter can realize stable 10 V output with constant output ripples when input voltage varies from 15 to 30 V. The output and ripples remain stable with varying load resistance. When subjected to over-current incident, the fabricated power IC can be protected according to desired over-current threshold values. The experiment results have demonstrated the functionality and feasibility of all GaN power ICs in power conversion applications.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"603 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116360479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 11
Differential Variable Base Charge Pumping ($Delta-text{CP}$) for SiO2/SiC Interface Characterization 差分可变基电荷泵送($Delta-text{CP}$)用于SiO2/SiC界面表征
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757560
P. Moens, A. Constant, A. Stockman, J. Franchi, F. Allerstam
{"title":"Differential Variable Base Charge Pumping ($Delta-text{CP}$) for SiO2/SiC Interface Characterization","authors":"P. Moens, A. Constant, A. Stockman, J. Franchi, F. Allerstam","doi":"10.1109/ISPSD.2019.8757560","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757560","url":null,"abstract":"We propose an electrical evaluation technique named differential charge pumping ($Delta-mathbf{CP}$) to extract information on the interface states (Dit) at the SiC/SiO2 interface. This technique allows to obtain information on (1) the physical location of the Dit; (2) the energetic spread of the Dit in the bandgap; (3) if the Dit are donor or acceptor type. First results indicate contributions from both the “S/D” region and the channel regions to the overall CP signal. Surprisingly a substantial contribution of the “S/D” regions of the transistors to the overall CP signal is observed. In the channel region, both donors and acceptor type states are identified, the majority being acceptor type.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"127 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116702566","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An Integrated Packaging Structure of Press Pack for High Power IGBTs 大功率igbt压片集成封装结构研究
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757672
E. Deng, B. Ren, Anqi Li, Yanhao Wang, Zhibin Zhao, Yongzhang Huang
{"title":"An Integrated Packaging Structure of Press Pack for High Power IGBTs","authors":"E. Deng, B. Ren, Anqi Li, Yanhao Wang, Zhibin Zhao, Yongzhang Huang","doi":"10.1109/ISPSD.2019.8757672","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757672","url":null,"abstract":"An Integrated packaging structure of press pack for high power IGBTs is proposed, in view of the shortcomings of Pedestal and Stakpak press pack IGBTs. The simplified model of the three packaging structures were simulated by finite element method. The simulation results reveal the pressure distribution on chip surfaces of the Integrated press pack IGBT is obviously better than the Pedestal one though slightly worse than the Stakpak one. Furthermore, the thermal dissipation ability of the integrated press pack IGBT is the best among the three packaging structures with lowest temperature and uniform temperature distribution. The Integrated packaging structure proposed in this paper meets the expected design requirements with uniform pressure distribution and lower junction temperature.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115684075","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
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