发布求助
文献互助 智能选刊 最新文献

2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)最新文献

筛选
英文 中文
A Total Ionizing Dose Detecting Circuit Based on Off-state Leakage Current of NLDMOS in Power IC 基于大功率集成电路NLDMOS断态泄漏电流的总电离剂量检测电路
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757653
Ping Luo, Rongxun Ling, Xiao Zhou, P. Jiang, Yucao Wu
{"title":"A Total Ionizing Dose Detecting Circuit Based on Off-state Leakage Current of NLDMOS in Power IC","authors":"Ping Luo, Rongxun Ling, Xiao Zhou, P. Jiang, Yucao Wu","doi":"10.1109/ISPSD.2019.8757653","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757653","url":null,"abstract":"Due to the demand of aerospace applications, radiation-hard techniques have become critical for power IC. In order to compensate the total ionizing dose (TID) effect on the circuits, detecting it is the precondition. The TID detecting circuit proposed in this paper is able to monitor the TID effect on power IC accurately in the radiated environment. Moreover, it can be integrated with conventional power IC in an ordinary commercial process. Namely, the signals generated by the detecting circuit can be applied to TID compensation for power IC flexibly. The simulation results of the detecting circuit can meet the design requirements accurately from radiation experiment.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122048719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Self-Turn-on-Free 5V Gate Driving for 1200V Scaled IGBT 1200V比例IGBT自导通5V栅极驱动
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757665
M. Tsukuda, Masaki Sudo, K. Hasegawa, S. Abe, T. Saraya, T. Takakura, M. Fukui, K. Itou, S. Suzuki, K. Takeuchi, T. Ninomiya, T. Hiramoto, I. Omura
{"title":"Self-Turn-on-Free 5V Gate Driving for 1200V Scaled IGBT","authors":"M. Tsukuda, Masaki Sudo, K. Hasegawa, S. Abe, T. Saraya, T. Takakura, M. Fukui, K. Itou, S. Suzuki, K. Takeuchi, T. Ninomiya, T. Hiramoto, I. Omura","doi":"10.1109/ISPSD.2019.8757665","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757665","url":null,"abstract":"Negative biasing of the gate voltage in a scaled insulated gate bipolar transistor (IGBT) during the off-state was modeled and found to be effective against self-turn-on failures. The required self-turn-on-free criteria were verified experimentally.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125628269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Impact of three-dimensional current flow on accurate TCAD simulation for trench-gate IGBTs 三维电流对沟栅igbt精确TCAD仿真的影响
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757640
Masahiro Watanabe, N. Shigyo, T. Hoshii, K. Furukawa, K. Kakushima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, A. Nakajima, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai
{"title":"Impact of three-dimensional current flow on accurate TCAD simulation for trench-gate IGBTs","authors":"Masahiro Watanabe, N. Shigyo, T. Hoshii, K. Furukawa, K. Kakushima, K. Satoh, T. Matsudai, T. Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, K. Takeuchi, I. Muneta, H. Wakabayashi, A. Nakajima, S. Nishizawa, K. Tsutsui, T. Hiramoto, H. Ohashi, H. Iwai","doi":"10.1109/ISPSD.2019.8757640","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757640","url":null,"abstract":"TCAD simulation has been recognized as a powerful design tool for insulated gate bipolar transistors (IGBTs). In this work, excellent agreement between 3D TCAD simulations and experimental current-voltage characteristics were obtained in the up to 1000 A/cm2 region for IGBTs with scaled trench-gates. The results of 2D and 3D simulations are compared to discuss the difference in current-voltage characteristics and their physical origins. A method to evaluate the saturation current ($boldsymbol{J}_{mathbf{Csat}}$) using a 2D simulation is also presented with an appropriate correction.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129495478","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Experimental Investigations of SiC MOSFETs under Short-Circuit Operations 短路工作下SiC mosfet的实验研究
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757644
Lei Cao, Zijian Gao, Qing Guo, Kuang Sheng
{"title":"Experimental Investigations of SiC MOSFETs under Short-Circuit Operations","authors":"Lei Cao, Zijian Gao, Qing Guo, Kuang Sheng","doi":"10.1109/ISPSD.2019.8757644","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757644","url":null,"abstract":"The short-circuit capability of power MOSFETs is crucial for the fault protection. In this work, short-circuit ruggedness and failure mechanisms of SiC planar and trench MOSFETs are compared and analyzed. Single-event short circuit tests are demonstrated. Experimental results show that thermal effect and gate stress are the two important factors which result in performance degradation and damage of SiC MOSFETs under short circuit operations. High gate stress will lead to hot carrier injection effect as well as tunneling effect under strong perpendicular electric field. The high current density and electric field at Pwell/Ndrift junction cause a high junction temperature, eventually leading to device failure. A temperature limited single-event failure SOA and drive-voltage limited degradation SOA are demonstrated.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126287977","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Experimental and Numerical Investigations of Short-Circuit Failure Mechanisms for State-of-the-Art 1.2kV SiC Trench MOSFETs 最新1.2kV SiC沟槽mosfet短路失效机理的实验与数值研究
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757617
M. Okawa, R. Aiba, T. Kanamori, H. Yano, N. Iwamuro, S. Harada
{"title":"Experimental and Numerical Investigations of Short-Circuit Failure Mechanisms for State-of-the-Art 1.2kV SiC Trench MOSFETs","authors":"M. Okawa, R. Aiba, T. Kanamori, H. Yano, N. Iwamuro, S. Harada","doi":"10.1109/ISPSD.2019.8757617","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757617","url":null,"abstract":"This paper is focused on the short-circuit capability and analysis of failure mechanism on relatively small DC power supply voltage for state-of-the-art 1.2 kV SiC trench MOSFETs. It is found that the gate-source SiO2 rapture could be a failure mechanism unique to the SiC MOSFETs. Further, the SiC trench MOSFETs with higher threshold voltage can effectively improve the short-circuit capabilities by reducing the probability of channel normally-on induced by the higher lattice temperature.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130913971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
An Experimentally Verified 3.3 kV SiC MOSFET Model Suitable for High-Current Modules Design 实验验证3.3 kV SiC MOSFET模型适合大电流模块设计
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757576
A. Borghese, M. Riccio, L. Maresca, G. Breglio, A. Irace, G. Romano, E. Bianda, A. Mihaila, M. Bellini, L. Knoll, S. Wirths
{"title":"An Experimentally Verified 3.3 kV SiC MOSFET Model Suitable for High-Current Modules Design","authors":"A. Borghese, M. Riccio, L. Maresca, G. Breglio, A. Irace, G. Romano, E. Bianda, A. Mihaila, M. Bellini, L. Knoll, S. Wirths","doi":"10.1109/ISPSD.2019.8757576","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757576","url":null,"abstract":"In this study, an electrothermal compact model for SiC power MOSFETs is experimentally verified for the first time on a 3.3 kV device. Both the parameters determining the static behavior and those controlling the dynamic performances are calibrated over experimental data. The good agreement achieved proves the model scalability form 1.2 kV devices to 3.3 kV ones. Successively, to validate the good convergence properties of the model, an electrothermal simulation of a three-phase inverter consisting of 36 hard switched MOSFETs is performed.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Power Cycling Test on 3.3kV SiC MOSFETs and the Effects of Bipolar Degradation on the Temperature Estimation by VSD-Method 3.3kV SiC mosfet功率循环试验及双极退化对vsd法温度估计的影响
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757588
F. Hoffmann, V. Soler, A. Mihaila, N. Kaminski
{"title":"Power Cycling Test on 3.3kV SiC MOSFETs and the Effects of Bipolar Degradation on the Temperature Estimation by VSD-Method","authors":"F. Hoffmann, V. Soler, A. Mihaila, N. Kaminski","doi":"10.1109/ISPSD.2019.8757588","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757588","url":null,"abstract":"In this work the impact of bipolar degradation on the temperature estimation during power cycling of high voltage SiC MOSFETs by means of the body-diode voltage drop is investigated. The results indicate that the voltage drop is subject to drift for devices prone to bipolar degradation even at moderate current densities in the regime of common sensing currents for the VSD-method. Hence, the criteria of the sensing current for the VSD-method are not only good sensitivity and linearity while avoiding self-heating but must consider possible drift of the calibration curve.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121853909","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Experiments of a Novel low on-resistance LDMOS with 3-D Floating Vertical Field Plate 新型低导通LDMOS三维浮动垂直场板实验研究
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757659
Guangsheng Zhang, Wentong Zhang, Junqing He, Xuhan Zhu, Sen Zhang, Jingchuan Zhao, Zhili Zhang, M. Qiao, Xin Zhou, Zhaoji Li, Bo Zhang
{"title":"Experiments of a Novel low on-resistance LDMOS with 3-D Floating Vertical Field Plate","authors":"Guangsheng Zhang, Wentong Zhang, Junqing He, Xuhan Zhu, Sen Zhang, Jingchuan Zhao, Zhili Zhang, M. Qiao, Xin Zhou, Zhaoji Li, Bo Zhang","doi":"10.1109/ISPSD.2019.8757659","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757659","url":null,"abstract":"A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with three-dimensional floating vertical field plate (3-D F-VFP) is proposed in this paper. The 3-D F-VFP LDMOS features a discrete pillar-type VFP array through the N-type drift region and the VFP pillars with the same distance from the source are connected to each other to realize the equal potential. In the off-state, the potential along the drift region are pinned by the series of equal-potential F-VFP rings and a new full-region depletion mode is introduced into the bulk of the device. Therefore, the highly doped drift region is depleted by the 3-D F-VFP, establishing a self-adaptive charge balance inside the drift region. In the on-state, the current flows through the gaps among all the F-VFP pillars, preventing the long current path and reducing the on resistance $boldsymbol{R}_{mathbf{on}}$. A 3-D F-VFP LDMOS is experimentally implemented, which obtains a breakdown voltage $boldsymbol{V}_{mathbf{B}}$ of 630 V and a $boldsymbol{R}_{mathbf{on}}$ of $344.8 mathbf{Omega}$ compared with 550 V and $722.5 mathbf{Omega}$ of the device without the F-VFP. The measured saturation current of the 3-D F-VFP LDMOS is more than 4.5 times of that of the device without F-VFP.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"83 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124806402","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Surge Current Capability of GaN E-HEMTs in Reverse Conduction Mode 反导模式下GaN e - hemt的浪涌电流性能
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757634
Yinxiang Liu, Shaowen Han, Shu Yang, Kuang Sheng
{"title":"Surge Current Capability of GaN E-HEMTs in Reverse Conduction Mode","authors":"Yinxiang Liu, Shaowen Han, Shu Yang, Kuang Sheng","doi":"10.1109/ISPSD.2019.8757634","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757634","url":null,"abstract":"In this paper, we investigate the surge current capability of two types of commercial GaN enhancement-mode HEMTs (E-HEMTs) in the reverse conduction mode, and reveal the impacts of the p-GaN technology and gate-to-source voltage ($boldsymbol{V}_{mathbf{GS}}$). The surge current capability of GaN E-HEMT can be enhanced with ohmic p-GaN contact and positive $boldsymbol{V}_{mathbf{GS}}$, owing to higher efficiency of hole injection and channel modulation. To our best knowledge, it is the first report to study the surge current capability and to reveal its underlying mechanisms in lateral GaN power devices.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125388830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Channel-off Avalanche Instability in SOI Lateral IGBT at Low Temperature: Mechanism and Optimization Schemes 低温下SOI横向IGBT的断道雪崩不稳定性:机制和优化方案
2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2019-05-01 DOI: 10.1109/ISPSD.2019.8757611
Jie Ma, Long Zhang, Jing Zhu, Shilin Cao, Ankang Li, Yanqin Zou, Weifeng Sun, Yan Gu, Sen Zhang, Yunwu Zhang, Zhuo Yang
{"title":"Channel-off Avalanche Instability in SOI Lateral IGBT at Low Temperature: Mechanism and Optimization Schemes","authors":"Jie Ma, Long Zhang, Jing Zhu, Shilin Cao, Ankang Li, Yanqin Zou, Weifeng Sun, Yan Gu, Sen Zhang, Yunwu Zhang, Zhuo Yang","doi":"10.1109/ISPSD.2019.8757611","DOIUrl":"https://doi.org/10.1109/ISPSD.2019.8757611","url":null,"abstract":"In this paper, the off-state avalanche stability is investigated and a time-dependent avalanche instability is observed at −40°C in SOI lateral IGBT. Combining results from measurements with those from TCAD simulations, the mechanism for avalanche instability is revealed. Two optimization schemes are proposed to suppress or eliminate the unstable avalanche phenomenon. The unstable avalanche can be suppressed by employing a thick buried oxide layer and VCE shift can be reduced from 54V to 11V. Another scheme is that replacing P-type substrate by N-type substrate, and then VCE shift can be completely eliminated.","PeriodicalId":225029,"journal":{"name":"2019 31st International Symposium on Power Semiconductor Devices and ICs (ISPSD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127768757","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
首页 上一页 下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：604180095
Book学术官方微信
小红书