Experiments of a Novel low on-resistance LDMOS with 3-D Floating Vertical Field Plate

Abstract

A novel lateral double-diffused metal–oxide semiconductor (LDMOS) with three-dimensional floating vertical field plate (3-D F-VFP) is proposed in this paper. The 3-D F-VFP LDMOS features a discrete pillar-type VFP array through the N-type drift region and the VFP pillars with the same distance from the source are connected to each other to realize the equal potential. In the off-state, the potential along the drift region are pinned by the series of equal-potential F-VFP rings and a new full-region depletion mode is introduced into the bulk of the device. Therefore, the highly doped drift region is depleted by the 3-D F-VFP, establishing a self-adaptive charge balance inside the drift region. In the on-state, the current flows through the gaps among all the F-VFP pillars, preventing the long current path and reducing the on resistance $\boldsymbol{R}_{\mathbf{on}}$. A 3-D F-VFP LDMOS is experimentally implemented, which obtains a breakdown voltage $\boldsymbol{V}_{\mathbf{B}}$ of 630 V and a $\boldsymbol{R}_{\mathbf{on}}$ of $344.8\ \mathbf{\Omega}$ compared with 550 V and $722.5\ \mathbf{\Omega}$ of the device without the F-VFP. The measured saturation current of the 3-D F-VFP LDMOS is more than 4.5 times of that of the device without F-VFP.