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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献

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Automatic synthesis of interfaces between incompatible protocols 自动合成不兼容协议之间的接口
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277047
R. Passerone, J. Rowson, A. Sangiovanni-Vincentelli
{"title":"Automatic synthesis of interfaces between incompatible protocols","authors":"R. Passerone, J. Rowson, A. Sangiovanni-Vincentelli","doi":"10.1145/277044.277047","DOIUrl":"https://doi.org/10.1145/277044.277047","url":null,"abstract":"At the system level, reusable Intellectual Property (or IP) blocks can be represented abstractly as blocks that exchange messages. The concrete implementations of these IP blocks must exchange the messages through complex signaling protocols. Interfacing between IP that use different signaling protocols is a tedious and error prone design task. We propose using regular expression based protocol descriptions to show how to map the message onto a signaling protocol. Given two protocols, an algorithm is proposed to build an interface machine. We have implemented our algorithm in a program named PIG that synthesizes a Verilog implementation based on a regular expression protocol description.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130912576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 180
Fault-simulation based design error diagnosis for sequential circuits 基于故障仿真的顺序电路设计错误诊断
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724548
Shi-Yu Huang, K. Cheng, Kuang-Chien Chen, J. Lu
{"title":"Fault-simulation based design error diagnosis for sequential circuits","authors":"Shi-Yu Huang, K. Cheng, Kuang-Chien Chen, J. Lu","doi":"10.1109/DAC.1998.724548","DOIUrl":"https://doi.org/10.1109/DAC.1998.724548","url":null,"abstract":"This paper addresses the problem of locating design errors in a sequential circuit. For single-error circuits, we consider a signal f as a potential error source only if the circuit can be completely rectified by re-synthesizing f (i.e., changing the function of signal f). In order to handle larger circuits, we do not rely on Binary Decision Diagram. Instead, we search for potential error sources by a modified sequential fault simulation process. The main contributions of this paper are two-fold: (1) we derive the necessary and sufficient condition of whether an erroneous input sequence (i.e., an input sequence producing erroneous responses) can be corrected by changing the function of a particular internal signal; and (2) we propose a modified fault simulation procedure to check this condition. Our approach does not rely on any error model, and thus, is suitable for general types of errors. Furthermore, it can be easily extended to identify multiple errors. Experimental results on ISCAS89 benchmark circuits are presented to demonstrate its capability.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128710551","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 32
Performance driven multi-layer general area routing for PCB/MCM designs 用于PCB/MCM设计的性能驱动的多层通用布线
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277144
J. Cong, P. Madden
{"title":"Performance driven multi-layer general area routing for PCB/MCM designs","authors":"J. Cong, P. Madden","doi":"10.1145/277044.277144","DOIUrl":"https://doi.org/10.1145/277044.277144","url":null,"abstract":"We present a new global router appropriate for Multichip Module (MCM) and dense Printed Circuit Board (PCB) design, which utilizes a hybrid of the classical rip-up and reroute approach, and the more recent iterative deletion method. The global router addresses performance issues by utilizing recent results in high performance interconnect design, while still effectively minimizing global congestion. With experiments on the maze-routing component of our global router, we show that the choice of routing cost functions can have a significant impact on final solution quality. The results of a number of previously proposed routers may be improved dramatically by adopting the cost functions we suggest here. We also find little evidence of the \"net ordering problem\" when our cost functions and routing model are applied. The iterative deletion method is shown to improve global solution quality, particularly when high performance interconnect is required. We evaluate the performance of our global router by comparing the congestion of routes produced by our global router to those of a well known MCM router, V4R. Our global router, MINOTAUR, supports arbitrary numbers of routing layers, differing capacities for each layer, preexisting congestion and obstacles, and high performance interconnect structures (including those which require variable width interconnect).","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"41 5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121230129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 58
Don't care-based BDD minimization for embedded software 不要对嵌入式软件进行基于关心的BDD最小化
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724524
Youpyo Hong, P. Beerel, L. Lavagno, E. Sentovich
{"title":"Don't care-based BDD minimization for embedded software","authors":"Youpyo Hong, P. Beerel, L. Lavagno, E. Sentovich","doi":"10.1109/DAC.1998.724524","DOIUrl":"https://doi.org/10.1109/DAC.1998.724524","url":null,"abstract":"This paper explores the use of don't cares in software synthesis for embedded systems. Embedded systems have extremely tight real-time and code/data size constraints, that make expensive optimizations desirable. We propose applying BDD minimization techniques in the presence of a don't care set to synthesize code for extended Finite State Machines from a BDD-based representation of the FSM transition function. The don't care set can be derived from local analysis (such as unused state codes or don't care inputs) as well as from external information (such as impossible input patterns). We show experimental results discuss their implications, the interaction between BDD-based minimization and dynamic variable reordering, and propose directions for future work.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122263470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Extending moment computation to 2-port circuit representations 将矩计算扩展到2端口电路表示
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724518
Fang-Jou Liu, Chung-Kuan Cheng
{"title":"Extending moment computation to 2-port circuit representations","authors":"Fang-Jou Liu, Chung-Kuan Cheng","doi":"10.1109/DAC.1998.724518","DOIUrl":"https://doi.org/10.1109/DAC.1998.724518","url":null,"abstract":"In this paper, we present an extension of moment computation to 2-port circuits. Our formulas are applicable to both transfer function moments and driving-point admittance moments. Given the input admittances, output admittances, and transfer functions of two 2-ports, our formulas compute the input admittance, output admittance, and transfer function when these 2-ports are combined either in parallel or in series. A nice conclusion of our work is the discovery our formulas form an elegant framework integrating the results from two classical papers. Rubinstein et al. and O'Brien and Savarino, for computing the Elmore delay and driving-point admittance moments in RC trees.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"159 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116427913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Design reliability-estimation through statistical analysis of bug discovery data 通过bug发现数据的统计分析来估计设计可靠性
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277209
Y. Malka, A. Ziv
{"title":"Design reliability-estimation through statistical analysis of bug discovery data","authors":"Y. Malka, A. Ziv","doi":"10.1145/277044.277209","DOIUrl":"https://doi.org/10.1145/277044.277209","url":null,"abstract":"Statistical analysis of bug discovery data is used in the software industry to check the quality of the testing process and estimate the reliability of the tested program. In this paper, we show that the same techniques are applicable to hardware design verification. We performed a study on two implementations of state-of-the-art PowerPC processors that shows that these techniques can provide quality information on the progress of verification and good predictions of the number of bugs left in the design and the future MTTF.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"11 suppl_1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126790388","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
PRIMO: probability interpretation of moments for delay calculation 用于延迟计算的力矩的概率解释
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277172
R. Kay, L. Pileggi
{"title":"PRIMO: probability interpretation of moments for delay calculation","authors":"R. Kay, L. Pileggi","doi":"10.1145/277044.277172","DOIUrl":"https://doi.org/10.1145/277044.277172","url":null,"abstract":"Moments of the impulse response are widely used for interconnect delay analysis, from the explicit Elmore delay (first moment of the impulse response) expression, to moment matching methods which create reduced order transimpedance and transfer function approximations. However the Elmore delay is fast becoming ineffective for deep submicron technologies, and reduced order transfer function delays are impractical for use as early-phase design metrics or as design optimization cost functions. This paper describes an approach for fitting moments of the impulse response to probability density functions so that delays can be estimated from probability tables. For RC trees it is demonstrated that the incomplete gamma function provides a provably stable approximation. The step response delay is obtained from a one-dimensional table lookup.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127228128","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 89
Enhanced visibility and performance in functional verification by reconstruction 通过重构增强功能验证的可见性和性能
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277083
Joshua Marantz
{"title":"Enhanced visibility and performance in functional verification by reconstruction","authors":"Joshua Marantz","doi":"10.1145/277044.277083","DOIUrl":"https://doi.org/10.1145/277044.277083","url":null,"abstract":"Cycle simulators, in-circuit emulators, and hardware accelerators have made it possible to rapidly model the functionality of large digital designs. But these techniques provide limited visibility of internal design nodes, making debugging hard. Simulators run slowly when all nodes are traced. Emulators provide full visibility only with limited depth, or with greatly reduced speed. This paper discusses software techniques for increasing design visibility while reducing tracing overhead in simulation, and achieving 100% visibility in emulation without reducing speed or compromising depth.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132649279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
System-chip test strategies 系统芯片测试策略
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277234
Y. Zorian
{"title":"System-chip test strategies","authors":"Y. Zorian","doi":"10.1145/277044.277234","DOIUrl":"https://doi.org/10.1145/277044.277234","url":null,"abstract":"A major challenge in realizing core-based system-chips is the adoption of adequate test and diagnosis strategies. This paper focuses on the current industrial practices in test strategies for system-chips. It discusses the challenges in testing embedded cores, the testing requirements for individual cores, and their test access mechanisms. It also covers the integrated test strategies for system-chips based on reusable cores. In addition to the state-of-the-art practices in testability schemes, this paper covers the current standardization efforts for embedded core test interface mechanisms.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130406703","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 31
Figures of merit to characterize the importance of on-chip inductance 图的优点，以表征片上电感的重要性
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277193
Y. Ismail, E. Friedman, J. Neves
{"title":"Figures of merit to characterize the importance of on-chip inductance","authors":"Y. Ismail, E. Friedman, J. Neves","doi":"10.1145/277044.277193","DOIUrl":"https://doi.org/10.1145/277044.277193","url":null,"abstract":"A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line, AS/X circuit simulations of an RLC transmission line and a five section RC II circuit based on a 0.25 /spl mu/m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it is shown that under certain conditions, inductance effects are negligible despite the length of the section of interconnect.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127960021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 288
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