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Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)最新文献

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Fast exact minimization of BDDs 快速精确地最小化bdd
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277099
R. Drechsler, Nicole Drechsler, Wolfgang Günther
{"title":"Fast exact minimization of BDDs","authors":"R. Drechsler, Nicole Drechsler, Wolfgang Günther","doi":"10.1145/277044.277099","DOIUrl":"https://doi.org/10.1145/277044.277099","url":null,"abstract":"We present a new exact algorithm for finding the optimal variable ordering for reduced ordered Binary Decision Diagrams (BDDs). The algorithm makes use of a lower bound technique known from VLSI design. Up to now this technique has been used only for theoretical considerations and if is adapted here for our purpose. Furthermore, the algorithm supports symmetry aspects and makes use of a hashing based data structure. Experimental results are given to demonstrate the efficiency of our approach. We succeeded in minimizing adder functions with up to 64 variables, while all other previously presented approaches fail.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134320107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 65
Phase noise in oscillators: a unifying theory and numerical methods for characterisation 振荡器中的相位噪声:表征的统一理论和数值方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277050
A. Demir, A. Mehrotra, J. Roychowdhury
{"title":"Phase noise in oscillators: a unifying theory and numerical methods for characterisation","authors":"A. Demir, A. Mehrotra, J. Roychowdhury","doi":"10.1145/277044.277050","DOIUrl":"https://doi.org/10.1145/277044.277050","url":null,"abstract":"Phase noise is a topic of theoretical and practical interest in electronic circuits, as well as in other fields such as optics. Although progress has been made in understanding the phenomenon, there still remain significant gaps, both in its fundamental theory and in numerical techniques for its characterisation. In this paper, we develop a solid foundation for phase noise that is valid for any oscillator, regardless of operating mechanism. We establish novel results about the dynamics of stable nonlinear oscillators in the presence of perturbations, both deterministic and random. We obtain an exact, nonlinear equation for phase error, which we solve without approximations for random perturbations. This leads us to a precise characterisation of timing jitter and spectral dispersion, for computing which we develop efficient numerical methods. We demonstrate our techniques on practical electrical oscillators, and obtain good matches with measurements even at frequencies close to the carrier, where previous techniques break down.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132409092","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 156
Layout techniques for minimizing on-chip interconnect self-inductance 最小化片上互连自感的布局技术
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277194
Y. Massoud, S. S. Majors, T. Bustami, Jacob K. White
{"title":"Layout techniques for minimizing on-chip interconnect self-inductance","authors":"Y. Massoud, S. S. Majors, T. Bustami, Jacob K. White","doi":"10.1145/277044.277194","DOIUrl":"https://doi.org/10.1145/277044.277194","url":null,"abstract":"Because magnetic effects have a much longer spatial range than electrostatic effects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it difficult to balance delays in nets like clock trees, so for such nets inductance must be minimized. In this paper we use two- and three-dimensional electromagnetic field solvers to compare dedicated ground planes to a less area-consuming approach, interdigitating the signal line with ground lines. The surprising conclusion is that with very little area penalty, interdigitated ground lines are more effective at minimizing self-inductance than ground planes.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"4 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113960276","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 137
ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models ftd:一个精确的频率到时间域转换为降低顺序的RLC互连模型
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724517
Y. Liu, L. Pileggi, A. Strojwas
{"title":"ftd: an exact frequency to time domain conversion for reduced order RLC interconnect models","authors":"Y. Liu, L. Pileggi, A. Strojwas","doi":"10.1109/DAC.1998.724517","DOIUrl":"https://doi.org/10.1109/DAC.1998.724517","url":null,"abstract":"Recursive convolution provides an exact solution for interfacing reduced-order frequency domain representations with discrete time domain models of piecewise linear voltage waveforms. The state-space method is more efficient, but not exact, and can sometimes produce large time domain errors. This paper presents a new algorithm, ftd (frequency to time domain), for incorporating linear frequency domain macro-models into time domain simulators. ftd provides accuracy equivalent to recursive convolution with efficiency that is superior to the state-space methods.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123725255","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
The DT-model: high-level synthesis using data transfers dt模型:使用数据传输的高级综合
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724450
Shantanu Tarafdar, M. Leeser
{"title":"The DT-model: high-level synthesis using data transfers","authors":"Shantanu Tarafdar, M. Leeser","doi":"10.1109/DAC.1998.724450","DOIUrl":"https://doi.org/10.1109/DAC.1998.724450","url":null,"abstract":"We present a new model for formulating the classic HLS subproblems: scheduling, allocation, and binding. The model is unique in its use of data-transfers as the basic entity in synthesis. A data transfer represents the movement of one instance of data and contains the operation sourcing the data and all the operations using it. Our model compels the storage architecture of the design to be optimized concurrently with the execution unit. We have built a high-level synthesis system, Midas, based on our data transfer model. Midas generates designs with smaller storage and data transfer requirements than other HLS systems.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122416763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
Design and optimization of low voltage high performance dual threshold CMOS circuits 低电压高性能双阈值CMOS电路的设计与优化
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1109/DAC.1998.724521
Liqiong Wei, Zhanping Chen, Mark C. Johnson, K. Roy, V. De
{"title":"Design and optimization of low voltage high performance dual threshold CMOS circuits","authors":"Liqiong Wei, Zhanping Chen, Mark C. Johnson, K. Roy, V. De","doi":"10.1109/DAC.1998.724521","DOIUrl":"https://doi.org/10.1109/DAC.1998.724521","url":null,"abstract":"Reduction in leakage power has become an important concern in low voltage, low power and high performance applications. In this paper, we use dual threshold technique to reduce leakage power by assigning high threshold voltage to some transistors in non-critical paths, and using low-threshold transistors in critical paths. In order to achieve the best leakage power saving under target performance constraints, an algorithm is presented for selecting and assigning an optimal high threshold voltage. A general standby leakage current model which has been verified by HSPICE is used to estimate standby leakage power. Results show that dual threshold technique is good for power reduction during both standby and active modes. The standby leakage power savings for some ISCAS benchmarks can be more than 50%.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734468","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 233
Technology mapping for large complex PLDs 大型复杂pld的技术映射
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277220
J. Anderson, S. Brown
{"title":"Technology mapping for large complex PLDs","authors":"J. Anderson, S. Brown","doi":"10.1145/277044.277220","DOIUrl":"https://doi.org/10.1145/277044.277220","url":null,"abstract":"In this paper we present a new technology mapping algorithm for use with complex PLDs (CPLDs), which consist of a large number of PLA-style logic blocks. Although the traditional synthesis approach for such devices uses two-level minimization, the complexity of recently-produced CPLDs has resulted in a trend toward multi-level synthesis. We describe an approach that allows existing multi-level synthesis techniques to be adapted to produce circuits that are well-suited for implementation in CPLDs. Our algorithm produces circuits that require up to 90% fewer logic blocks than the circuits produced by a recently-published algorithm.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132740959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 51
Incremental CTL model checking using BDD subsetting 基于BDD子集的增量CTL模型检验
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277171
Abelardo Pardo, G. Hachtel
{"title":"Incremental CTL model checking using BDD subsetting","authors":"Abelardo Pardo, G. Hachtel","doi":"10.1145/277044.277171","DOIUrl":"https://doi.org/10.1145/277044.277171","url":null,"abstract":"An automatic abstraction/refinement algorithm for symbolic CTL model checking is presented. Conservative model checking is thus done for the full CTL language-no restriction is made to the universal or existential fragments. The algorithm begins with conservative verification of an initial abstraction. If the conclusion is negative, it derives a \"goal set\" of states which require further resolution. It then successively refines, with respect to this goal set, the approximations made in the sub-formulas, until the given formula is verified or computational resources are exhausted. This method applies uniformly to the abstractions based in over-approximation as well as under-approximations of the model. Both the refinement and the abstraction procedures are based in BDD-subsetting. Note that refinement procedures which are based on error traces, are limited to over-approximation on the universal fragment (or for language containment), whereas the goal set method is applicable to all consistent approximations, and for all CTL formulas.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131869132","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 47
Design methodologies for noise in digital integrated circuits 数字集成电路噪声的设计方法
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277062
K. Shepard
{"title":"Design methodologies for noise in digital integrated circuits","authors":"K. Shepard","doi":"10.1145/277044.277062","DOIUrl":"https://doi.org/10.1145/277044.277062","url":null,"abstract":"In this paper, we describe the growing problems of noise in digital integrated circuits and the design tools and techniques used to ensure the noise immunity of digital designs.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129994372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 96
Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor 多问题，无序，超标量Alpha处理器- DEC Alpha 21264微处理器的功能验证
Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175) Pub Date : 1998-05-01 DOI: 10.1145/277044.277208
Scott A. Taylor, M. Quinn, Darren Brown, Nathan Dohm, S. Hildebrandt, J. Huggins, Carl Ramey
{"title":"Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor","authors":"Scott A. Taylor, M. Quinn, Darren Brown, Nathan Dohm, S. Hildebrandt, J. Huggins, Carl Ramey","doi":"10.1145/277044.277208","DOIUrl":"https://doi.org/10.1145/277044.277208","url":null,"abstract":"DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the Alpha architecture, capable of a peak execution rate of six instructions per cycle and a sustainable rate of four per cycle. The 21264 also features a 500 MHz clock speed and a high-bandwidth system interface that channels up to 5.3 Gbytes/second of cache data and 2.6 Gbytes/second of main-memory data into the processor. Simulation-based functional verification was performed on the logic design using implementation-directed, pseudo-random exercisers, supplemented with implementation-specific, hand-generated tests. Extensive functional coverage analysis was performed to grade and direct the verification effort. The success of the verification effort was underscored by first prototype chips which were used to boot multiple operating systems across several different prototype systems.","PeriodicalId":221221,"journal":{"name":"Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130860318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 72
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