Functional verification of a multiple-issue, out-of-order, superscalar Alpha processor-the DEC Alpha 21264 microprocessor

Scott A. Taylor, M. Quinn, Darren Brown, Nathan Dohm, S. Hildebrandt, J. Huggins, Carl Ramey
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引用次数: 72

Abstract

DIGITAL's Alpha 21264 processor is a highly out-of-order, superpipelined, superscalar implementation of the Alpha architecture, capable of a peak execution rate of six instructions per cycle and a sustainable rate of four per cycle. The 21264 also features a 500 MHz clock speed and a high-bandwidth system interface that channels up to 5.3 Gbytes/second of cache data and 2.6 Gbytes/second of main-memory data into the processor. Simulation-based functional verification was performed on the logic design using implementation-directed, pseudo-random exercisers, supplemented with implementation-specific, hand-generated tests. Extensive functional coverage analysis was performed to grade and direct the verification effort. The success of the verification effort was underscored by first prototype chips which were used to boot multiple operating systems across several different prototype systems.
多问题,无序,超标量Alpha处理器- DEC Alpha 21264微处理器的功能验证
DIGITAL的Alpha 21264处理器是Alpha架构的高度乱序、超流水线、超标量实现,每个周期的峰值执行速率为6条指令,每个周期的可持续执行速率为4条指令。21264还具有500 MHz时钟速度和高带宽系统接口,可将高达5.3 gb /秒的缓存数据和2.6 gb /秒的主存数据传输到处理器中。对逻辑设计进行基于仿真的功能验证,使用面向实现的伪随机练习者,并辅以特定于实现的手工生成测试。执行广泛的功能覆盖分析来分级和指导验证工作。第一个原型芯片被用于跨几个不同的原型系统启动多个操作系统,从而强调了验证工作的成功。
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